Datasheet

45
9166DS–AVR-01/12
AT32UC3C
6. Supply and Startup Considerations
6.1 Supply Considerations
6.1.1 Power Supplies
The AT32UC3C has several types of power supply pins:
VDDIO pins (VDDIO1, VDDIO2, VDDIO3): Power I/O lines. Two voltage ranges are available: 5V or
3.3V nominal. The VDDIO pins should be connected together.
VDDANA: Powers the Analog part of the device (Analog I/Os, ADC, ACs, DACs). 2 voltage ranges
available: 5V or 3.3V nominal.
VDDIN_5: Input voltage for the 1.8V and 3.3V regulators. Two Voltage ranges are available: 5V or
3.3V nominal.
VDDIN_33:
USB I/O power supply
if the device is 3.3V powered: Input voltage, voltage is 3.3V nominal.
if the device is 5V powered: stabilization for the 3.3V voltage regulator, requires external
capacitors
VDDCORE: Stabilization for the 1.8V voltage regulator, requires external capacitors.
GNDCORE: Ground pins for the voltage regulators and the core.
GNDANA: Ground pin for Analog part of the design
GNDPLL: Ground pin for the PLLs
GNDIO pins (GNDIO1, GNDIO2, GNDIO3): Ground pins for the I/O lines. The GNDIO pins should be
connected together.
See ”Electrical Characteristics” on page 49 for power consumption on the various supply pins.
For decoupling recommendations for the different power supplies, please refer to the schematic
checklist.
6.1.2 Voltage Regulators
The AT32UC3C embeds two voltage regulators:
One 1.8V internal regulator that converts from VDDIN_5 to 1.8V. The regulator supplies the
output voltage on VDDCORE.
One 3.3V internal regulator that converts from VDDIN_5 to 3.3V. The regulator supplies the
USB pads on VDDIN_33. If the USB is not used or if VDDIN_5 is within the 3V range, the
3.3V regulator can be disabled through the VREG33CTL field of the VREGCTRL SCIF
register.
6.1.3 Regulators Connection
The AT32UC3C supports two power supply configurations.
5V single supply mode
3.3V single supply mode
6.1.3.1 5V Single Supply Mode
In 5V single supply mode, the 1.8V internal regulator is connected to the 5V source (VDDIN_5
pin) and its output feeds VDDCORE.