Datasheet

40
9166DS–AVR-01/12
AT32UC3C
5.2 Physical Memory Map
The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they
are never remapped in any way, not even in boot. Note that AVR32UC CPU uses unsegmented
translation, as described in the AVR32 Architecture Manual. The 32-bit physical address space
is mapped as follows:
5.3 Peripheral Address Map
Table 5-1. AT32UC3C Physical Memory Map
Device Start Address
AT32UC3 Derivatives
C0512C
C1512C
C2512C
C1256C
C2256C
C2128C
Embedded SRAM 0x0000_0000 64 KB 64 KB 64 KB 32 KB
Embedded Flash 0x8000_0000 512 KB 512 KB 256 KB 128 KB
SAU 0x9000_0000 1 KB 1 KB 1 KB 1 KB
HSB SRAM 0xA000_0000 4 KB 4 KB 4 KB 4 KB
EBI SRAM CS0 0xC000_0000 16 MB - - -
EBI SRAM CS2 0xC800_0000 16 MB - - -
EBI SRAM CS3 0xCC00_0000 16 MB - - -
EBI SRAM CS1
/SDRAM CS0
0xD000_0000 128 MB - - -
HSB-PB Bridge C 0xFFFD_0000 64 KB 64 KB 64 KB 64 KB
HSB-PB Bridge B 0xFFFE_0000 64 KB 64 KB 64 KB 64 KB
HSB-PB Bridge A 0xFFFF_0000 64 KB 64 KB 64 KB 64 KB
Table 5-2. Flash Memory Parameters
Part Number
Flash Size
(FLASH_PW)
Number of
pages
(FLASH_P)
Page size
(FLASH_W)
AT32UC3C0512C
AT32UC3C1512C
AT32UC3C2512C
512 Kbytes 1024 128 words
AT32UC3C1256C
AT32UC3C2256C
256 Kbytes 512 128 words
AT32UC3C2128C 128 Kbytes 256 128 words
Table 5-3. Peripheral Address Mapping
Address Peripheral Name
0xFFFD0000
PDCA Peripheral DMA Controller - PDCA