Datasheet

39
9166DS–AVR-01/12
AT32UC3C
5. Memories
5.1 Embedded Memories
• Internal High-Speed Flash (See Table 5-1 on page 40)
– 512 Kbytes
– 256 Kbytes
– 128 Kbytes
• 0 Wait State Access at up to 25 MHz in Worst Case Conditions
• 1 Wait State Access at up to 50 MHz in Worst Case Conditions
• Pipelined Flash Architecture, allowing burst reads from sequential Flash locations, hiding
penalty of 1 wait state access
• Pipelined Flash Architecture typically reduces the cycle penalty of 1 wait state operation
to only 15% compared to 0 wait state operation
• 10 000 Write Cycles, 15-year Data Retention Capability
• Sector Lock Capabilities, Bootloader Protection, Security Bit
• 32 Fuses, Erased During Chip Erase
• User Page For Data To Be Preserved During Chip Erase
• Internal High-Speed SRAM, Single-cycle access at full speed (See Table 5-1 on page 40)
– 64 Kbytes
– 32 Kbytes
• Supplementary Internal High-Speed System SRAM (HSB RAM), Single-cycle access at full speed
– Memory space available on System Bus for peripherals data.
– 4 Kbytes