Datasheet

22
9166DS–AVR-01/12
AT32UC3C
RX_CLK Receive Clock Input
RX_DV Receive Data Valid Input
RX_ER Receive Coding Error Input
SPEED Speed Output
TXD[3:0] Transmit Data Output
TX_CLK Transmit Clock or Reference Clock Input
TX_EN Transmit Enable Output
TX_ER Transmit Coding Error Output
WOL Wake-On-LAN Output
Peripheral Event Controller - PEVC
PAD_EVT[15:0] Event Input Pins Input
Power Manager - PM
RESET_N Reset Pin Input Low
Pulse Width Modulator - PWM
PWMH[3:0]
PWML[3:0]
PWM Output Pins Output
EXT_FAULT[1:0] PWM Fault Input Pins Input
Quadrature Decoder- QDEC0/QDEC1
QEPA QEPA quadrature input Input
QEPB QEPB quadrature input Input
QEPI Index input Input
System Controller Interface- SCIF
XIN0, XIN1, XIN32 Crystal 0, 1, 32K Inputs Analog
XOUT0, XOUT1,
XOUT32
Crystal 0, 1, 32K Output Analog
GCLK0 - GCLK1 Generic Clock Pins Output
Serial Peripheral Interface - SPI0, SPI1
MISO Master In Slave Out I/O
MOSI Master Out Slave In I/O
Table 3-7. Signal Description List
Signal Name Function Type
Active
Level Comments