Datasheet

9166DS–AVR-01/12

AT32UC3C

10.2 rev D

10.2.1 ADCIFA

1 ADCREFP/ADCREFN can not be selected as an external ADC reference by setting the

ADCIFA.CFG.EXREF bit to one

Fix/Workaround

A voltage reference can be applied on ADCREFP/ADCREFN pins if the

ADCIFA.CFG.EXREF bit is set to zero, the ADCIFA.CFG.RS bit is set to zero and the volt-

age reference applied on ADCREFP/ADCREFN pins is higher than the internal 1V

reference.

10.2.2 AST

1 AST wake signal is released one AST clock cycle after the BUSY bit is cleared

After writing to the Status Clear Register (SCR) the wake signal is released one AST clock

cycle after the BUSY bit in the Status Register (SR.BUSY) is cleared. If entering sleep mode

directly after the BUSY bit is cleared the part will wake up immediately.

Fix/Workaround

Read the Wake Enable Register (WER) and write this value back to the same register. Wait

for BUSY to clear before entering sleep mode.

10.2.3 aWire

1 aWire MEMORY_SPEED_REQUEST command does not return correct CV

The aWire MEMORY_SPEED_REQUEST command does not return a CV corresponding to

the formula in the aWire Debug Interface chapter.

Fix/Workaround

Issue a dummy read to address 0x100000000 before issuing the

MEMORY_SPEED_REQUEST command and use this formula instead:

10.2.4 GPIO

1 Clearing Interrupt flags can mask other interrupts

When clearing interrupt flags in a GPIO port, interrupts on other pins of that port, happening

in the same clock cycle will not be registered.

Fix/Workaround

Read the PVR register of the port before and after clearing the interrupt to see if any pin

change has happened while clearing the interrupt. If any change occurred in the PVR

between the reads, they must be treated as an interrupt.

10.2.5 Power Manager

1 Clock Failure Detector (CFD) can be issued while turning off the CFD

While turning off the CFD, the CFD bit in the Status Register (SR) can be set. This will

change the main clock source to RCSYS.

Fix/Workaround

Solution 1: Enable CFD interrupt. If CFD interrupt is issues after turning off the CFD, switch

back to original main clock source.

Solution 2: Only turn off the CFD while running the main clock on RCSYS.

sab

CV 3–

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