Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 100 (14x14) 32-Bit 66 MHz I/O number 81

NOTE: This is a summary document.

The complete document is available on

the Atmel website at www.atmel.com.

Features

• High Performance, Low Power 32-bit AVR

Microcontroller

– Compact Single-cycle RISC Instruction Set Including DSP Instruction Set

– Built-in Floating-Point Processing Unit (FPU)

– Read-Modify-Write Instructions and Atomic Bit Manipulation

– Performing 1.49 DMIPS / MHz

• Up to 68 DMIPS Running at 50 MHz from Flash (1 Wait-State)

• Up to 37 DMIPS Running at 25 MHz from Flash (0 Wait-State)

– Memory Protection Unit

• Multi-hierarchy Bus System

– High-Performance Data Transfers on Separate Buses for Increased Performance

– 16 Peripheral DMA Channels Improves Speed for Peripheral Communication

• Internal High-Speed Flash

– 512 Kbytes, 256 Kbytes, 128 Kbytes Versions

– Single Cycle Access up to 25 MHz

–FlashVault

™

Technology Allows Pre-programmed Secure Library Support for End

User Applications

– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed

– 10,000 Write Cycles, 15-year Data Retention Capability

– Flash Security Locks and User Defined Configuration Area

• Internal High-Speed SRAM, Single-Cycle Access at Full Speed

– 64 Kbytes (512 KB and 256 KB Flash), 32 Kbytes (128 KB Flash)

– 4 Kbytes on the Multi-Layer Bus System (HSB RAM)

• External Memory Interface on AT32UC3C0 Derivatives

– SDRAM / SRAM Compatible Memory Bus (16-bit Data and 24-bit Address Buses)

• Interrupt Controller

– Autovectored Low Latency Interrupt Service with Programmable Priority

• System Functions

– Power and Clock Manager

– Internal 115KHz (RCSYS) and 8MHz/1MHz (RC8M) RC Oscillators

– One 32 KHz and Two Multipurpose Oscillators

– Clock Failure detection

– Two Phase-Lock-Loop (PLL) allowing Independent CPU Frequency from USB or

CAN Frequency

• Windowed Watchdog Timer (WDT)

• Asynchronous Timer (AST) with Real-Time Clock Capability

– Counter or Calendar Mode Supported

• Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency

• Ethernet MAC 10/100 Mbps interface

– 802.3 Ethernet Media Access Controller

– Supports Media Independent Interface (MII) and Reduced MII (RMII)

• Universal Serial Bus (USB)

– Device 2.0 and Embedded Host Low Speed and Full Speed

– Flexible End-Point Configuration and Management with Dedicated DMA Channels

– On-chip Transceivers Including Pull-Ups

• One 2-channel Controller Area Network (CAN)

– CAN2A and CAN2B protocol compliant, with high-level mailbox system

– Two independent channels, 16 Message Objects per Channel

9166DS–AVR–01/12

32-bit AVR

Microcontroller

AT32UC3C0512C

AT32UC3C1512C

AT32UC3C1256C

AT32UC3C2512C

AT32UC3C2256C

AT32UC3C2128C

Automotive

Summary

Summary of content (109 pages)

PAGE 1
Features • High Performance, Low Power 32-bit AVR® Microcontroller – – – – • • • • • • • • • • • • Compact Single-cycle RISC Instruction Set Including DSP Instruction Set Built-in Floating-Point Processing Unit (FPU) Read-Modify-Write Instructions and Atomic Bit Manipulation Performing 1.
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AT32UC3C • One 4-Channel 20-bit Pulse Width Modulation Controller (PWM) • • • • • • • • • • • • • • – Complementary outputs, with Dead Time Insertion – Output Override and Fault Protection Two Quadrature Decoders One 16-channel 12-bit Pipelined Analog-To-Digital Converter (ADC) – Dual Sample and Hold Capability Allowing 2 Synchronous Conversions – Single-Ended and Differential Channels, Window Function Two 12-bit Digital-To-Analog Converters (DAC), with Dual Output Sample System Four Analog Compara
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AT32UC3C 1. Description The AT32UC3C is a complete System-On-Chip microcontroller based on the AVR32UC RISC processor running at frequencies up to 50 MHz. AVR32UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density and high performance.
PAGE 4
AT32UC3C The Full-Speed USB 2.0 Device interface supports several USB Classes at the same time thanks to the rich End-Point configuration. The On-The-GO (OTG) Host interface allows device like a USB Flash disk or a USB printer to be directly connected to the processor. The media-independent interface (MII) and reduced MII (RMII) 10/100 Ethernet MAC module provides on-chip solutions for network-connected devices.
PAGE 5
AT32UC3C 2. Overview Block diagram Block diagram TDO TCK TDI TMS AVR32UC CPU JTAG INTERFACE NEXUS CLASS 2+ OCD MCKO MDO[5..0] MSEO[1..0] EVTI_N EVTO_N VBUS D+ DID VBOF USB INTERFACE M Flash Controller 512/ 256/ 128/64 KB Flash M S S M W M R M S M M PBB HSB PB S CONFIGURATION PERIPHERAL DMA CONTROLLER S REGISTERS HSB Memory DMA COL, CRS, RXD[3..0], RX_CLK, RX_DV, RX_ER, TX_CLK DMA BUS HSB PB HSB-PB BRIDGE B HSB-PB BRIDGE A DATA[15..0] ADDR[23..0] NCS[3..
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AT32UC3C 2.2 Configuration Summary Table 2-1.
PAGE 7
AT32UC3C Table 2-1.
PAGE 8
AT32UC3C 3. Package and Pinout 3.1 Package The device pins are multiplexed with peripheral functions as described in Table 3-1 on page 11. QFN64/TQFP64 Pinout 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PD01 PD00 PC22 PC21 PC20 PC19 PC18 PC17 PC16 PC15 PC05 PC04 GNDIO2 VDDIO2 PC03 PC02 Figure 3-1.
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AT32UC3C TQFP100 Pinout 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PD01 PD00 PC31 PC24 PC23 PC22 PC21 PC20 PC19 PC18 PC17 PC16 PC15 PC14 PC13 PC12 PC11 PC07 PC06 PC05 PC04 GNDIO2 VDDIO2 PC03 PC02 Figure 3-2.
PAGE 10
AT32UC3C LQFP144 Pinout 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 PD01 PD00 PC31 PC30 GNDIO3 VDDIO3 PC29 PC28 PC27 PC26 PC25 PC24 PC23 PC22 PC21 PC20 PC19 PC18 PC17 PC16 PC15 PC14 PC13 PC12 PC11 PC10 PC09 PC08 PC07 PC06 PC05 PC04 GNDIO2 VDDIO2 PC03 PC02 Figure 3-3.
PAGE 11
AT32UC3C 3.2 Peripheral Multiplexing on I/O lines 3.2.1 Multiplexed Signals Each GPIO line can be assigned to one of the peripheral functions. The following table describes the peripheral signals multiplexed to the GPIO lines. Table 3-1.
PAGE 12
AT32UC3C Table 3-1.
PAGE 13
AT32UC3C Table 3-1.
PAGE 14
AT32UC3C Table 3-1.
PAGE 15
AT32UC3C Table 3-1.
PAGE 16
AT32UC3C Table 3-1.
PAGE 17
AT32UC3C 3.2.2 Peripheral Functions Each GPIO line can be assigned to one of several peripheral functions. The following table describes how the various peripheral functions are selected. The last listed function has priority in case multiple functions are enabled on the same pin. Table 3-2. 3.2.
PAGE 18
AT32UC3C depending on the configuration of the OCD AXS register. For details, see the AVR32UC Technical Reference Manual. Table 3-5. 3.2.
PAGE 19
AT32UC3C Table 3-7. Signal Description List Signal Name Active Level Function Type 1.8V Voltage Regulator Input Power Input Power Supply: 4.5V to 5.5V or 3.0V to 3.6 V VDDIN_33 USB I/O power supply Power Output/ Input Capacitor Connection for the 3.3V voltage regulator or power supply: 3.0V to 3.6 V VDDCORE 1.8V Voltage Regulator Output Power output Capacitor Connection for the 1.
PAGE 20
AT32UC3C Table 3-7.
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AT32UC3C Table 3-7.
PAGE 22
AT32UC3C Table 3-7.
PAGE 23
AT32UC3C Table 3-7.
PAGE 24
AT32UC3C Table 3-7. Signal Description List Signal Name Function DP USB Device Port Data + Analog VBUS USB VBUS Monitor and OTG Negociation Analog Input ID ID Pin of the USB Bus Input VBOF USB VBUS On/off: bus power control port output 3.4 3.4.1 Type Active Level Comments I/O Line Considerations JTAG pins The JTAG is enabled if TCK is low while the RESET_N pin is released. The TCK, TMS, and TDI pins have pull-up resistors when JTAG is enabled.
PAGE 25
AT32UC3C 4. Processor and Architecture Rev: 2.1.2.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, and MPU is presented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical Reference Manual. 4.1 Features • 32-bit load/store AVR32A RISC architecture – – – – – • • • • 4.
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AT32UC3C single cycle. Load and store instructions have several different formats in order to reduce code size and speed up execution. The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values from function calls and is used implicitly by some instructions. 4.
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AT32UC3C OCD interface Reset interface Overview of the AVR32UC CPU Interrupt controller interface Figure 4-1. OCD system Power/ Reset control AVR32UC CPU pipeline MPU 4.3.
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AT32UC3C Figure 4-2. The AVR32UC Pipeline MUL IF ID Prefetch unit Decode unit Regfile Read ALU LS 4.3.2 4.3.2.1 Multiply unit Regfile write ALU unit Load-store unit AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is targeted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt contexts.
PAGE 29
AT32UC3C 4.3.2.5 Unaligned Reference Handling AVR32UC does not support unaligned accesses, except for doubleword accesses. AVR32UC is able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an address exception. Doubleword-sized accesses with word-aligned pointers will automatically be performed as two word-sized accesses. The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Table 4-1. 4.3.2.
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AT32UC3C 4.4 4.4.1 Programming Model Register File Configuration The AVR32UC register file is shown below. Figure 4-3.
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AT32UC3C Figure 4-5. The Status Register Low Halfword Bit 15 Bit 0 - T - - - - - - - - L Q V N Z C Bit name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value Carry Zero Sign Overflow Saturation Lock Reserved Scratch Reserved 4.4.3 4.4.3.1 Processor States Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 4-2. Table 4-2. Overview of Execution Modes, their Priorities and Privilege Levels.
PAGE 32
AT32UC3C Debug state can be entered as described in the AVR32UC Technical Reference Manual. Debug state is exited by the retd instruction. 4.4.3.3 4.4.4 Secure State The AVR32 can be set in a secure state, that allows a part of the code to execute in a state with higher security levels. The rest of the code can not access resources reserved for this secure code. Secure State is used to implement FlashVault technology. Refer to the AVR32UC Technical Reference Manual for details.
PAGE 33
AT32UC3C Table 4-3.
PAGE 34
AT32UC3C Table 4-3. 4.
PAGE 35
AT32UC3C relative to EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception code segments must be set up appropriately. The same mechanisms are used to service all different types of events, including interrupt requests, yielding a uniform event handling scheme.
PAGE 36
AT32UC3C 4.5.3 Supervisor Calls The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is designed so that privileged routines can be called from any context. This facilitates sharing of code between different execution modes. The scall mechanism is designed so that a minimal execution cycle overhead is experienced when performing supervisor routine calls from timecritical event handlers.
PAGE 37
AT32UC3C than the oldest instruction. An instruction B is younger than an instruction A if it was sent down the pipeline later than A. The addresses and priority of simultaneous events are shown in Table 4-4 on page 38. Some of the exceptions are unused in AVR32UC since it has no MMU, coprocessor interface, or floatingpoint unit.
PAGE 38
AT32UC3C Table 4-4.
PAGE 39
AT32UC3C 5. Memories 5.
PAGE 40
AT32UC3C 5.2 Physical Memory Map The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot. Note that AVR32UC CPU uses unsegmented translation, as described in the AVR32 Architecture Manual. The 32-bit physical address space is mapped as follows: Table 5-1.
PAGE 41
AT32UC3C Table 5-3.
PAGE 42
AT32UC3C Table 5-3.
PAGE 43
AT32UC3C Table 5-3. Peripheral Address Mapping 0xFFFF6000 ACIFA0 Analog Comparators Interface - ACIFA0 ACIFA1 Analog Comparators Interface - ACIFA1 0xFFFF6400 0xFFFF6800 DACIFB0 DAC interface - DACIFB0 DACIFB1 DAC interface - DACIFB1 0xFFFF6C00 0xFFFF7000 AW 5.4 aWire - AW CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being mapped on the Peripheral Bus.
PAGE 44
AT32UC3C Table 5-4.
PAGE 45
AT32UC3C 6. Supply and Startup Considerations 6.1 6.1.1 Supply Considerations Power Supplies The AT32UC3C has several types of power supply pins: • VDDIO pins (VDDIO1, VDDIO2, VDDIO3): Power I/O lines. Two voltage ranges are available: 5V or 3.3V nominal. The VDDIO pins should be connected together. • VDDANA: Powers the Analog part of the device (Analog I/Os, ADC, ACs, DACs). 2 voltage ranges • • • • • • • available: 5V or 3.3V nominal. VDDIN_5: Input voltage for the 1.8V and 3.3V regulators.
PAGE 46
AT32UC3C The 3.3V regulator is connected to the 5V source (VDDIN_5 pin) and its output feeds the USB pads. If the USB is not used, the 3.3V regulator can be disabled through the VREG33CTL field of the VREGCTRL SCIF register. Figure 6-1 on page 46 shows the power schematics to be used for 5V single supply mode. All I/O lines and analog blocks will be powered by the same power (VDDIN_5 = VDDIO1 = VDDIO2 = VDDIO3 = VDDANA). Figure 6-1. 5V Single Power Supply mode + 4.55.
PAGE 47
AT32UC3C Figure 6-2. 3 Single Power Supply Mode + 3.03.6V CIN2 VDDIO1 VDDIO2 VDDIO3 VDDIN_5 VDDANA GNDANA CIN1 BOD33 Analog: ADC, AC, DAC, ... BOD50 3.3V Reg VDDIN_33 VDDCORE COUT2 1.8V Reg COUT1 CPU Peripherals Memories GNDIO1 GNDIO2 GNDIO3 SCIF, BOD, RCSYS GNDPLL PLL BOD18 GNDCORE POR 6.1.4 6.1.4.1 Power-up Sequence Maximum Rise Rate To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values described in Table 7-2 on page 50.
PAGE 48
AT32UC3C 6.2 Startup Considerations This chapter summarizes the boot sequence of the AT32UC3C. The behavior after power-up is controlled by the Power Manager. For specific details, refer to the Power Manager chapter. 6.2.1 Starting of clocks At power-up, the BOD33 and the BOD18 are enabled. The device will be held in a reset state by the power-up circuitry, until the VDDIN_33 (resp. VDDCORE) has reached the reset threshold of the BOD33 (resp BOD18).
PAGE 49
AT32UC3C 7. Electrical Characteristics 7.1 Absolute Maximum Ratings* Operating temperature................................... -40°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied.
PAGE 50
AT32UC3C Table 7-2. Supply Rise Rates and Order Rise Rate Symbol Parameter Min Max VVDDIN_5 DC supply internal 3.3V regulator 0.01 V/ms 1.25 V/us VVDDIN_33 DC supply internal 1.8V regulator 0.01 V/ms 1.25 V/us VVDDIO1 VVDDIO2 VVDDIO3 DC supply peripheral I/O 0.01 V/ms 1.25 V/us Rise after or at the same time as VDDIN_5, VDDIN_33 VVDDANA DC supply peripheral I/O and analog part 0.01 V/ms 1.25 V/us Rise after or at the same time as VDDIN_5, VDDIN_33 7.
PAGE 51
AT32UC3C – Internal 3.3V regulator is off • TA = 25°C • I/Os are configured as inputs, with internal pull-up enabled. • Oscillators – OSC0/1 (crystal oscillator) stopped – OSC32K (32KHz crystal oscillator) stopped – PLL0 running – PLL1 stopped • Clocks – External clock on XIN0 as main clock source (10MHz) – CPU, HSB, and PBB clocks undivided – PBA, PBC clock divided by 4 – All peripheral clocks running Table 7-4.
PAGE 52
AT32UC3C Figure 7-1. Measurement Schematic VDDANA VDDIO Amp VDDIN_5 VDDIN_33 VDDCORE GNDCORE GNDPLL 7.4.1 Peripheral Power Consumption The values in Table 7-5 are measured values of power consumption under the following conditions. • Operating conditions core supply (Figure 7-1) – VVDDIN_5 = VDDIN_33 = 3.3V – VVDDCORE = 1.85V , supplied by the internal regulator – VVDDIO1 = VVDDIO2 = VVDDIO3 = 3.3V – VVDDANA = 3.3V – Internal 3.3V regulator is off.
PAGE 53
AT32UC3C – PLL1 stopped • Clocks – External clock on XIN0 as main clock source. – CPU, HSB, and PB clocks undivided Consumption active is the added current consumption when the module clock is turned on and when the module is doing a typical set of operations. Table 7-5. Peripheral Typical Current Consumption by Peripheral(2) Typ Consumption Active (1) ACIFA (1) 3 ADCIFA 7 AST 3 CANIF 25 DACIFB(1) 3 EBI 23 EIC 0.5 FREQM 0.
PAGE 54
AT32UC3C 7.5 I/O Pin Characteristics Normal I/O Pin Characteristics(1) Table 7-6. Symbol Parameter RPULLUP Pull-up resistance RPULLDOWN Pull-down resistance VIL Input low-level voltage VIH Input high-level voltage Condition Min VVDD = 3V VVDD = 5V Typ Max Units 5 26 kOhm 5 16 kOhm 2 16 kOhm VVDD = 3V 0.3*VVDDIO VVDD = 4.5V 0.3*VVDDIO VVDD = 3.6V 0.7*VVDDIO VVDD = 5.5V 0.7*VVDDIO V V IOL = -3.
PAGE 55
AT32UC3C Normal I/O Pin Characteristics(1) Table 7-6. Symbol Parameter Condition VVDD = 3.0V tRISE Rise time(3) VVDD = 4.5V VVDD = 3.0V tFALL Fall time(3) VVDD = 4.5V ILEAK CIN Min Max load = 10pF, pin drive x1 8.4 load = 10pF, pin drive x2 (2) 3.8 load = 10pF, pin drive x4 (2) 2.1 load = 30pF, pin drive x1(2) 17.5 load = 30pF, pin drive x2(2) 8.2 load = 30pF, pin drive x4 (2) 4.2 load = 10pF, pin drive x1 (2) 5.9 load = 10pF, pin drive x2(2) 2.
PAGE 56
AT32UC3C 7.6 Oscillator Characteristics 7.6.1 7.6.1.1 Oscillator (OSC0 and OSC1) Characteristics Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN0 or XIN1. Table 7-7. Digital Clock Characteristics Symbol Parameter fCPXIN XIN clock frequency tCPXIN XIN clock period tCHXIN XIN clock high half-priod 0.4 x tCPXIN 0.6 x tCPXIN ns tCLXIN XIN clock low half-priod 0.4 x tCPXIN 0.
PAGE 57
AT32UC3C Table 7-8. Crystal Oscillator Characteristics Symbol Parameter fOUT Crystal oscillator frequency Ci Internal equivalent load capacitance tSTARTUP Notes: Conditions Min Typ 0.4 Max Unit 20 MHz 1.7 pF fOUT = 8MHz SCIF.OSCCTRL.GAIN = 1(1) 975 us fOUT = 16MHz SCIF.OSCCTRL.GAIN = 2(1) 1100 us Startup time 1. Please refer to the SCIF chapter for details. 7.6.2 32KHz Crystal Oscillator (OSC32K) Characteristics 7.6.2.
PAGE 58
AT32UC3C 7.6.3 Phase Lock Loop (PLL0 and PLL1) Characteristics Table 7-11. PLL Characteristics Symbol Parameter fVCO Output frequency fIN Input frequency IPLL Current consumption tSTARTUP Startup time, from enabling the PLL until the PLL is locked 7.6.
PAGE 59
AT32UC3C 7.7 Flash Characteristics Table 7-15 gives the device maximum operating frequency depending on the number of flash wait states. The FSW bit in the FLASHC FSR register controls the number of wait states used when accessing the flash memory. Table 7-15. Maximum Operating Frequency Flash Wait States Read Mode Maximum Operating Frequency 0 1 cycle 25MHz 1 2 cycles 50MHz Table 7-16.
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AT32UC3C 7.8 Analog Characteristics 7.8.1 1.8V Voltage Regulator Characteristics Table 7-18. 1.8V Voltage Regulator Electrical Characteristics Symbol Parameter VVDDIN_5 Input voltage range VVDDCORE Output voltage, calibrated value IOUT DC output current Table 7-19. Condition Min Typ Max 5V range 4.5 5.5 3V range 3.0 3.6 Units V 1.85 V 80 mA Decoupling Requirements Symbol Parameter CIN1 Typ Techno.
PAGE 61
AT32UC3C 7.8.4 3.3V Brown Out Detector (BOD33) Characteristics The values in Table 7-23 describe the values of the BOD33.LEVEL field in the SCIF module. Table 7-23. BOD33.LEVEL Values BOD33.LEVEL Value Parameter Min Max 17 2.27 2.52 22 2.36 2.61 27 2.45 2.71 2.52 2.79 33 2.56 2.83 39 2.67 2.95 44 2.76 3.05 49 2.85 3.15 53 2.91 3.23 60 3.05 3.37 31 threshold at power-up sequence Units V 7.8.
PAGE 62
AT32UC3C 7.8.6 Analog to Digital Converter (ADC) and sample and hold (S/H) Characteristics Table 7-27. Symbol fADC ADC and S/H characteristics Parameter ADC clock frequency Conditions Min Typ 12-bit resolution mode, VVDDANA = 3V 1.2 10-bit resolution mode, VVDDANA = 3V 1.6 8-bit resolution mode, VVDDANA = 3V 2.2 12-bit resolution mode, VVDDANA = 4.5V 1.5 10-bit resolution mode, VVDDANA = 4.5V 2 8-bit resolution mode, VVDDANA = 4.5V 2.
PAGE 63
AT32UC3C Table 7-29. ADC Decoupling requirements Symbol Parameter Conditions CADCREFPN ADCREFP/ADCREFN capacitance No voltage reference appplied on ADCREFP/ADCREFN Table 7-30. Min Typ Max 100 Units nF ADC Inputs Symbol Parameter VADCINn ADC input voltage range Conditions CONCHIP Internal Capacitance RONCHIP Switch resistance Figure 7-3. Min Typ 0 Max Units VVDDANA V ADC used without S/H 5 ADC used with S/H 4 ADC used without S/H 5.1 ADC used with S/H 4.
PAGE 64
AT32UC3C Table 7-31. Symbol ADC Transfer Characteristics (Continued)12-bit Resolution Mode(1) Parameter Conditions Differential mode, VVDDANA = 5V, VADCREF0 = 3V, ADCFIA.SEQCFGn.SRES = 0 (Fadc = 1.5MHz) RES Resolution INL Integral Non-Linearity DNL Differential Non-Linearity Offset error Gain error Note: Max Units 12 Bit 5 LSB 4 LSB -20 20 mV -30 30 mV Max Units 10 Bit 1.
PAGE 65
AT32UC3C Table 7-34. ADC and S/H Transfer Characteristics 12-bit Resolution Mode and S/H gain = 1(1) Symbol Parameter Conditions RES Resolution INL Integral Non-Linearity Differential mode, VVDDANA = 3V, VADCREF0 = 1V, ADCFIA.SEQCFGn.SRES = 0, S/H gain = 1 (Fadc = 1.2MHz) DNL Differential Non-Linearity Offset error Gain error RES Resolution INL Integral Non-Linearity DNL Differential Non-Linearity Offset error Gain error Note: Differential mode, VVDDANA = 5V, VADCREF0 = 3V, ADCFIA.
PAGE 66
AT32UC3C Table 7-36. ADC and S/H Transfer Characteristics (Continued)10-bit Resolution Mode and S/H gain from 1 to 16(1) Symbol Parameter Conditions Differential mode, VVDDANA = 5V, VADCREF0 = 3V, ADCFIA.SEQCFGn.SRES = 1, S/H gain from 1 to 16 (Fadc = 1.5MHz) RES Resolution INL Integral Non-Linearity DNL Differential Non-Linearity Offset error Gain error Note: Min Typ Max Units 10 Bit 2 LSB 2 LSB -30 30 mV -30 30 mV Max Units 1.
PAGE 67
AT32UC3C Figure 7-4. DAC output UC3C DAC0A S/H CLOAD DAC RLOAD Transfer Characteristics(1) Table 7-40.
PAGE 68
AT32UC3C 7.8.8 Analog Comparator Characteristics Analog Comparator Characteristics(1) Table 7-41.
PAGE 69
AT32UC3C 7.9 Timing Characteristics 7.9.1 Startup, Reset, and Wake-up Timing The startup, reset, and wake-up timings are calculated using the following formula: t = t CONST + N CPU × t CPU Where t CONST and N CPU are found in Table 7-44. t CONST is the delay relative to RCSYS, t CPU is the period of the CPU clock. If another clock source than RCSYS is selected as CPU clock the startup time of the oscillator, t OSCSTART , must be added to the wake-up time in the stop, deepstop, and static sleep modes.
PAGE 70
AT32UC3C Figure 7-5. Startup and Reset Time Voltage VDDIN_5, VDDIN_33 BOD33 threshold at power-up VDDCORE BOD18 threshold at power-up Time Internal Reset 7.9.2 Reset Time Startup Time from reset Release Decoding Stage RESET_N characteristics Table 7-45. RESET_N Clock Waveform Parameters Symbol Parameter tRESET RESET_N minimum pulse length Condition Min. 2 * TRCSYS Typ. Max.
PAGE 71
AT32UC3C 7.9.3 USART in SPI Mode Timing 7.9.3.1 Master mode Figure 7-6. USART in SPI Master Mode With (CPOL= CPHA= 0) or (CPOL= CPHA= 1) SPCK MISO USPI0 USPI1 MOSI USPI2 Figure 7-7. USART in SPI Master Mode With (CPOL= 0 and CPHA= 1) or (CPOL= 1 and CPHA= 0) SPCK MISO USPI3 USPI4 MOSI USPI5 Table 7-46.
PAGE 72
AT32UC3C Maximum SPI Frequency, Master Output The maximum SPI master output frequency is given by the following formula: 1 f CLKSPI × 2 f SPCKMAX = MIN (f PINMAX,------------, -----------------------------) SPIn 9 Where SPIn is the MOSI delay, USPI2 or USPI5 depending on CPOL and NCPHA. f PINMAX is the maximum frequency of the SPI pins. Please refer to the I/O Pin Characteristics section for the maximum frequency of the pins. f CLKSPI is the maximum frequency of the CLK_SPI.
PAGE 73
AT32UC3C Figure 7-9. USART in SPI Slave Mode With (CPOL= CPHA= 0) or (CPOL= CPHA= 1) SPCK MISO USPI9 MOSI USPI10 USPI11 Figure 7-10. USART in SPI Slave Mode NPCS Timing USPI12 USPI13 USPI14 USPI15 SPCK, CPOL=0 SPCK, CPOL=1 NSS Table 7-47.
PAGE 74
AT32UC3C Maximum SPI Frequency, Slave Input Mode The maximum SPI slave input frequency is given by the following formula: f CLKSPI × 2 1 f SPCKMAX = MIN (----------------------------,------------) 9 SPIn Where SPIn is the MOSI setup and hold time, USPI7 + USPI8 or USPI10 + USPI11 depending on CPOL and NCPHA. f CLKSPI is the maximum frequency of the CLK_SPI. Refer to the SPI chapter for a description of this clock.
PAGE 75
AT32UC3C Figure 7-12. SPI Master Mode With (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0) SPCK MISO SPI3 SPI4 MOSI SPI5 Table 7-48. SPI Timing, Master Mode(1) Symbol Parameter SPI0 MISO setup time before SPCK rises SPI1 MISO hold time after SPCK rises SPI2 SPCK rising to MOSI delay SPI3 MISO setup time before SPCK falls SPI4 MISO hold time after SPCK falls SPI5 SPCK falling to MOSI delay Note: Conditions external capacitor = 40pF Min Max Units 30.5+ (tCLK_SPI)/2 ns 0 ns 11.
PAGE 76
AT32UC3C 7.9.4.2 Slave mode Figure 7-13. SPI Slave Mode With (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0) SPCK MISO SPI6 MOSI SPI7 SPI8 Figure 7-14. SPI Slave Mode With (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1) SPCK MISO SPI9 MOSI SPI10 Figure 7-15.
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AT32UC3C Table 7-49. SPI Timing, Slave Mode(1) Symbol Parameter Conditions Min Max Units SPI6 SPCK falling to MISO delay 31 ns SPI7 MOSI setup time before SPCK rises 0 ns SPI8 MOSI hold time after SPCK rises 7 ns SPI9 SPCK rising to MISO delay SPI10 MOSI setup time before SPCK falls SPI11 MOSI hold time after SPCK falls SPI12 NPCS setup time before SPCK rises SPI13 32 external capacitor = 40pF ns 1.5 ns 5 ns 4 ns NPCS hold time after SPCK falls 2.
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AT32UC3C TWIM and TWIS user interface registers. Please refer to the TWIM and TWIS sections for more information. Table 7-50. TWI-Bus Timing Requirements Minimum Symbol Parameter Mode Requirement Standard(1) tr TWCK and TWD rise time tf TWCK and TWD fall time tHD-STA (Repeated) START hold time tSU-STA (Repeated) START set-up time tSU-STO STOP set-up time tHD-DAT Data hold time tLOW-I2C Standard(1) 4.0 Fast(1) 0.6 Standard(1) 4.7 Fast(1) 0.6 Standard(1) 4.0 Fast(1) 0.
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AT32UC3C 7.9.6 JTAG Timing Figure 7-16. JTAG Interface Signals JTAG2 TCK JTAG0 JTAG1 TMS/TDI JTAG3 JTAG4 JTAG7 JTAG8 TDO JTAG5 JTAG6 Boundary Scan Inputs Boundary Scan Outputs JTAG9 JTAG10 Table 7-51. JTAG Timings(1) Symbol Parameter JTAG0 TCK Low Half-period 23 ns JTAG1 TCK High Half-period 9 ns JTAG2 TCK Period 31 ns JTAG3 TDI, TMS Setup before TCK High 7 ns JTAG4 TDI, TMS Hold after TCK High 0 ns JTAG5 TDO Hold Time 13.
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AT32UC3C 7.9.7 EBI Timings See EBI I/O lines description for more details. Table 7-52. SMC Clock Signal. Symbol Parameter 1/(tCPSMC) SMC Controller clock frequency Note: Max(1) Units fcpu MHz 1. The maximum frequency of the SMC interface is the same as the max frequency for the HSB. SMC Read Signals with Hold Settings(1) Table 7-53.
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AT32UC3C SMC Read Signals with no Hold Settings(1) Table 7-54. Symbol Parameter Conditions Min Units NRD Controlled (READ_MODE = 1) SMC19 Data setup before NRD high SMC20 Data hold after NRD high VVDD = 3.0V, drive strength of the pads set to the lowest, external capacitor = 40pF 34.4 ns 0 NRD Controlled (READ_MODE = 0) SMC21 Data setup before NCS high SMC22 Data hold after NCS high Note: VVDD = 3.0V, drive strength of the pads set to the lowest, external capacitor = 40pF 30.2 ns 0 1.
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AT32UC3C SMC Write Signals with No Hold Settings (NWE Controlled only)(1) Table 7-56. Symbol Parameter SMC37 NWE rising to A2-A25 valid 9.1 SMC38 NWE rising to NBS0/A0 valid 7.9 SMC40 NWE rising to A1/NBS2 change SMC42 NWE rising to NCS rising SMC43 Data Out valid before NWE rising SMC44 Data Out valid after NWE rising SMC45 NWE pulse width Note: Conditions Min VVDD = 3.0V, drive strength of the pads set to the lowest, external capacitor = 40pF Units 9.1 8.
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AT32UC3C Figure 7-18. SMC Signals for NRD and NRW Controlled Accesses(1) SMC37 SMC7 SMC7 SMC31 A2-A25 SMC25 SMC26 SMC29 SMC30 SMC3 SMC4 SMC5 SMC6 SMC38 SMC39 SMC40 SMC41 SMC3 SMC4 SMC5 SMC6 A0/A1/NBS[3:0] SMC42 SMC32 SMC8 NCS SMC8 SMC9 SMC9 NRD SMC19 SMC20 SMC43 SMC44 SMC1 SMC23 SMC2 SMC24 D0 - D15 SMC45 SMC33 NWE Note: 7.9.8 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology.
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AT32UC3C Table 7-58. SDRAM Signal(1) Symbol Parameter Conditions Min SDRAMC1 SDCKE high before SDCK rising edge 7.7 SDRAMC2 SDCKE low after SDCK rising edge 10 SDRAMC3 SDCKE low before SDCK rising edge 8.8 SDRAMC4 SDCKE high after SDCK rising edge 10.9 SDRAMC5 SDCS low before SDCK rising edge 8.1 SDRAMC6 SDCS high after SDCK rising edge 11 SDRAMC7 RAS low before SDCK rising edge 9.1 SDRAMC8 RAS high after SDCK rising edge 10.3 SDRAMC9 SDA10 change before SDCK rising edge 8.
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AT32UC3C Figure 7-19. SDRAMC Signals relative to SDCK.
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AT32UC3C 7.9.9 MACB Characteristics Table 7-59. Symbol Ethernet MAC Signals(1) Parameter MAC1 Setup for MDIO from MDC rising MAC2 Hold for MDIO from MDC rising MAC3 MDIO toggling from MDC falling Note: Conditions Min. Max. Unit VVDD = 3.0V, drive strength of the pads set to the highest, external capacitor = 10pF on MACB pins 0 2.6 ns 0 0.7 ns 0 1.1 ns 1.
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AT32UC3C Figure 7-20.
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AT32UC3C Table 7-61. Symbol Ethernet MAC RMII Specific Signals(1) Parameter Conditions Min. Max. Unit MAC21 TX_EN toggling from TX_CLK rising 12.5 13.4 ns MAC22 TXD toggling from TX_CLK rising 12.5 13.4 ns MAC23 Setup for RXD from TX_CLK MAC24 Hold for RXD from TX_CLK MAC25 Setup for RX_ER from TX_CLK MAC26 Hold for RX_ER from TX_CLK MAC27 MAC28 Note: 4.7 ns 0 ns 3.6 ns 0 ns Setup for RX_DV from TX_CLK 4.6 ns Hold for RX_DV from TX_CLK 0 ns VVDD = 3.
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AT32UC3C 8. Mechanical Characteristics 8.1 8.1.1 Thermal Considerations Thermal Data Table 8-1 summarizes the thermal resistance data depending on the package. Table 8-1. 8.1.2 Thermal Resistance Data Symbol Parameter Condition Package Typ θJA Junction-to-ambient thermal resistance No air flow QFN64 20.0 θJC Junction-to-case thermal resistance QFN64 0.8 θJA Junction-to-ambient thermal resistance TQFP64 40.5 θJC Junction-to-case thermal resistance TQFP64 8.
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AT32UC3C 8.2 Package Drawings Figure 8-1. Note: QFN-64 package drawing The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability. Table 8-2. Device and Package Maximum Weight 200 Table 8-3. mg Package Characteristics Moisture Sensitivity Level Table 8-4.
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AT32UC3C Figure 8-2. TQFP-64 package drawing Table 8-5. Device and Package Maximum Weight 300 Table 8-6. mg Package Characteristics Moisture Sensitivity Level Table 8-7.
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AT32UC3C Figure 8-3. TQFP-100 package drawing Table 8-8. Device and Package Maximum Weight 500 Table 8-9. mg Package Characteristics Moisture Sensitivity Level Table 8-10.
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AT32UC3C Figure 8-4. LQFP-144 package drawing Table 8-11. Device and Package Maximum Weight 1300 Table 8-12. mg Package Characteristics Moisture Sensitivity Level Table 8-13.
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AT32UC3C 8.3 Soldering Profile Table 8-14 gives the recommended soldering profile from J-STD-20. Table 8-14. Soldering Profile Profile Feature Green Package Average Ramp-up Rate (217°C to Peak) 3°C/sec Preheat Temperature 175°C ±25°C Min. 150 °C, Max. 200 °C Temperature Maintained Above 217°C 60-150 sec Time within 5⋅C of Actual Peak Temperature 30 sec Peak Temperature Range 260 °C Ramp-down Rate 6 °C/sec Time 25⋅C to Peak Temperature Max.
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AT32UC3C 9. Ordering Information Table 9-1.
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AT32UC3C 10. Errata 10.1 10.1.1 10.1.2 10.1.3 rev E ADCIFA 1 ADCREFP/ADCREFN can not be selected as an external ADC reference by setting the ADCIFA.CFG.EXREF bit to one Fix/Workaround A voltage reference can be applied on ADCREFP/ADCREFN pins if the ADCIFA.CFG.EXREF bit is set to zero, the ADCIFA.CFG.RS bit is set to zero and the voltage reference applied on ADCREFP/ADCREFN pins is higher than the internal 1V reference.
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AT32UC3C 10.1.5 10.1.6 SCIF 1 PLLCOUNT value larger than zero can cause PLLEN glitch Initializing the PLLCOUNT with a value greater than zero creates a glitch on the PLLEN signal during asynchronous wake up. Fix/Workaround The lock-masking mechanism for the PLL should not be used. The PLLCOUNT field of the PLL Control Register should always be written to zero.
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AT32UC3C 10.1.7 10.1.8 4 SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and NCPHA=0 When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one (CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0, then an additional pulse will be generated on SCK. Fix/Workaround When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1 if CSRn.CPOL=1 and CSRn.NCPHA=0.
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AT32UC3C Fix/Workaround None. 10.1.11 3 In host mode, the disconnection during OUT transition is not supported In USB host mode, a pipe can not work if the previous USB device disconnection has occurred during a USB transfer. Fix/Workaround Reset the USBC (USBCON.USB=0 and =1) after a device disconnection (UHINT.DDISCI). 4 In USB host mode, entering suspend mode can fail In USB host mode, entering suspend mode can fail when UHCON.SOFE=0 is done just after a SOF reception (UHINT.HSOFI).
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AT32UC3C 10.2 10.2.1 10.2.2 10.2.3 rev D ADCIFA 1 ADCREFP/ADCREFN can not be selected as an external ADC reference by setting the ADCIFA.CFG.EXREF bit to one Fix/Workaround A voltage reference can be applied on ADCREFP/ADCREFN pins if the ADCIFA.CFG.EXREF bit is set to zero, the ADCIFA.CFG.RS bit is set to zero and the voltage reference applied on ADCREFP/ADCREFN pins is higher than the internal 1V reference.
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AT32UC3C 10.2.6 10.2.7 2 Requesting clocks in idle sleep modes will mask all other PB clocks than the requested In idle or frozen sleep mode, all the PB clocks will be frozen if the TWIS or the AST need to wake the cpu up. Fix/Workaround Disable the TWIS or the AST before entering idle or frozen sleep mode. 3 TWIS may not wake the device from sleep mode If the CPU is put to a sleep mode (except Idle and Frozen) directly after a TWI Start condition, the CPU may not wake upon a TWIS address match.
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AT32UC3C 10.2.8 10.2.9 2 Disabling SPI has no effect on the SR.TDRE bit Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer is empty, and this data will be lost. Fix/Workaround Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the SPI and PDCA.
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AT32UC3C 10.2.10 10.2.11 TWIS 1 Clearing the NAK bit before the BTF bit is set locks up the TWI bus When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Register (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to attempt to continue transmitting data, thus locking up the bus. Fix/Workaround Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been set.
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AT32UC3C 10.2.12 WDT 1 Clearing the Watchdog Timer (WDT) counter in second half of timeout period will issue a Watchdog reset If the WDT counter is cleared in the second half of the timeout period, the WDT will immediately issue a Watchdog reset. Fix/Workaround Use twice as long timeout period as needed and clear the WDT counter within the first half of the timeout period. If the WDT counter is cleared after the first half of the timeout period, you will get a Watchdog reset immediately.
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AT32UC3C 11. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 11.1 11.2 11.3 Rev. D – 01/12 1 Errata: Updated 2 PM: Clock Mask Table Updated 3 Fixed PLLOPT field description in SCIF chapter 4 MDMA: Swapped bit descriptions for IER and IDR 5 MACB: USRIO register description and bit descriptions for IMR/IDR/IER Updated 6 USBC: UPCON.
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AT32UC3C 11.4 4 SCIF: Added VREGCR register 5 AST: Updated digital tuner formula 6 SDRAMC: cleaned-up SDCS/NCS names. Added VERSION register 7 SAU: Updated SR.IDLE 8 USART: Updated 9 CANIF: Updated address map figure 10 USBC: Updated 11 DACIFB: Updated 12 Programming and Debugging: Added JTAG Data Registers section 13 Electrical Characteristics: Updated 14 Ordering Information: Updated 15 Errata: Updated 1 Initial revision Rev.
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AT32UC3C Table of Contents 1 2 3 4 5 6 7 Description ............................................................................................... 3 1.1 Disclaimer ..........................................................................................................4 1.2 Automotive Quality Grade .................................................................................4 Overview ................................................................................................... 5 2.
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AT32UC3C 8 9 7.7 Flash Characteristics .......................................................................................59 7.8 Analog Characteristics .....................................................................................60 7.9 Timing Characteristics .....................................................................................69 Mechanical Characteristics ................................................................... 89 8.1 Thermal Considerations ..................
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