Datasheet

32059L–AVR32–01/2012

AT32UC3B

2. Transfer error will stall a transmit peripheral handshake interface

If a transfer error is encountered on a channel transmitting to a peripheral, the peripheral

handshake of the active channel will stall and the PDCA will not do any more transfers on

the affected peripheral handshake interface.

Fix/Workaround

Disable and then enable the peripheral after the transfer error.

3. TWI

4. The TWI RXRDY flag in SR register is not reset when a software reset is performed

The TWI RXRDY flag in SR register is not reset when a software reset is performed.

Fix/Workaround

After a Software Reset, the register TWI RHR must be read.

5. TWI in master mode will continue to read data

TWI in master mode will continue to read data on the line even if the shift register and the

RHR register are full. This will generate an overrun error.

Fix/Workaround

To prevent this, read the RHR register as soon as a new RX data is ready.

6. TWI slave behaves improperly if master acknowledges the last transmitted data byte

before a STOP condition

In I2C slave transmitter mode, if the master acknowledges the last data byte before a STOP

condition (what the master is not supposed to do), the following TWI slave receiver mode

frame may contain an inappropriate clock stretch. This clock stretch can only be stopped by

resetting the TWI.

Fix/Workaround

If the TWI is used as a slave transmitter with a master that acknowledges the last data byte

before a STOP condition, it is necessary to reset the TWI before entering slave receiver

mode.

7. TC

8. Channel chaining skips first pulse for upper channel

When chaining two channels using the Block Mode Register, the first pulse of the clock

between the channels is skipped.

Fix/Workaround

Configure the lower channel with RA = 0x1 and RC = 0x2 to produce a dummy clock cycle

for the upper channel. After the dummy cycle has been generated, indicated by the

SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real

values.

- OCD

1. The auxiliary trace does not work for CPU/HSB speed higher than 50MHz

The auxiliary trace does not work for CPU/HSB speed higher than 50MHz.

Fix/Workaround

Do not use the auxiliary trace for CPU/HSB speed higher than 50MHz.