Datasheet

53
32059L–AVR32–01/2012
AT32UC3B
Figure 9-10. SPI Slave mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1)
Notes: 1. 3.3V domain: V
VDDIO
from 3.0V to 3.6V, maximum external capacitor = 40 pF.
2. t
CPMCK
: Master Clock period in ns.
SPCK
MISO
MOSI
SPI
9
SPI
10
SPI
11
Table 9-27. SPI Timings
Symbol Parameter Conditions Min. Max. Unit
SPI
0
MISO Setup time before SPCK rises
(master)
3.3V domain
(1)
22 +
(t
CPMCK
)/2
(2)
ns
SPI
1
MISO Hold time after SPCK rises
(master)
3.3V domain
(1)
0ns
SPI
2
SPCK rising to MOSI Delay
(master)
3.3V domain
(1)
7ns
SPI
3
MISO Setup time before SPCK falls
(master)
3.3V domain
(1)
22 +
(t
CPMCK
)/2
(2)
ns
SPI
4
MISO Hold time after SPCK falls
(master)
3.3V domain
(1)
0ns
SPI
5
SPCK falling to MOSI Delay
master)
3.3V domain
(1)
7ns
SPI
6
SPCK falling to MISO Delay
(slave)
3.3V domain
(1)
26.5 ns
SPI
7
MOSI Setup time before SPCK rises
(slave)
3.3V domain
(1)
0ns
SPI
8
MOSI Hold time after SPCK rises
(slave)
3.3V domain
(1)
1.5 ns
SPI
9
SPCK rising to MISO Delay
(slave)
3.3V domain
(1)
27 ns
SPI
10
MOSI Setup time before SPCK falls
(slave)
3.3V domain
(1)
0ns
SPI
11
MOSI Hold time after SPCK falls
(slave)
3.3V domain
(1)
1ns