Datasheet

4
32059L–AVR32–01/2012
AT32UC3B
2. Overview
2.1 Blockdiagram
Figure 2-1. Block diagram
TIMER/COUNTER
INTERRUPT
CONTROLLER
REAL TIME
COUNTER
PERIPHERAL
DMA
CONTROLLER
HSB-PB
BRIDGE B
HSB-PB
BRIDGE A
S
MM M
S
S
M
EXTERNAL
INTERRUPT
CONTROLLER
HIGH SPEED
BUS MATRIX
GENERAL PURPOSE IOs
GENERAL PURPOSE IOs
PA
PB
A[2..0]
B[2..0]
CLK[2..0]
EXTINT[7..0]
KPS[7..0]
NMI
GCLK[3..0]
XIN32
XOUT32
XIN0
XOUT0
P
A
P
B
RESET_N
32 KHz
OSC
115 kHz
RCOSC
OSC0
PLL0
SERIAL
PERIPHERAL
INTERFACE
TWO-WIRE
INTERFACE
PDCPDC
MISO, MOSI
NPCS[3..0]
SCL
SDA
USART1
PDC
RXD
TXD
CLK
RTS, CTS
DSR, DTR, DCD, RI
USART0
USART2
PDC
RXD
TXD
CLK
RTS, CTS
SYNCHRONOUS
SERIAL
CONTROLLER
PDC
TX_CLOCK, TX_FRAME_SYNC
RX_DATA
TX_DATA
RX_CLOCK, RX_FRAME_SYNC
ANALOG TO
DIGITAL
CONVERTER
PDC
AD[7..0]
ADVREF
WATCHDOG
TIMER
XIN1
XOUT1
OSC1
PLL1
SCK
JTAG
INTERFACE
MCKO
MDO[5..0]
MSEO[1..0]
EVTI_N
TCK
TDO
TDI
TMS
POWER
MANAGER
RESET
CONTROLLER
SLEEP
CONTROLLER
CLOCK
CONTROLLER
CLOCK
GENERATOR
CONFIGURATION REGISTERS BUS
PB
PB
HSB
HSB
S
FLASH
CONTROLLER
M
S
USB
INTERFACE
DMA
ID
VBOF
VBUS
D-
D+
EVTO_N
AVR32 UC
CPU
NEXUS
CLASS 2+
OCD
INSTR
INTERFACE
DATA
INTERFACE
MEMORY INTERFACE
FAST GPIO
16/32/96 KB
SRAM
MEMORY PROTECTION UNIT
LOCAL BUS
INTERFACE
AUDIO
BITSTREAM
DAC
PDC
DATA[1..0]
DATAN[1..0]
PULSE WIDTH
MODULATION
CONTROLLER
PWM[6..0]
64/128/
256/512 KB
FLASH