Datasheet

31
32059L–AVR32–01/2012
AT32UC3B
7. Memories
7.1 Embedded Memories
• Internal High-Speed Flash
– 512KBytes (AT32UC3B0512, AT32UC3B1512)
– 256 KBytes (AT32UC3B0256, AT32UC3B1256)
– 128 KBytes (AT32UC3B0128, AT32UC3B1128)
– 64 KBytes (AT32UC3B064, AT32UC3B164)
• - 0 Wait State Access at up to 30 MHz in Worst Case Conditions
• - 1 Wait State Access at up to 60 MHz in Worst Case Conditions
• - Pipelined Flash Architecture, allowing burst reads from sequential Flash locations,
hiding penalty of 1 wait state access
• - 100 000 Write Cycles, 15-year Data Retention Capability
• - 4 ms Page Programming Time, 8 ms Chip Erase Time
• - Sector Lock Capabilities, Bootloader Protection, Security Bit
• - 32 Fuses, Erased During Chip Erase
• - User Page For Data To Be Preserved During Chip Erase
• Internal High-Speed SRAM, Single-cycle access at full speed
– 96KBytes ((AT32UC3B0512, AT32UC3B1512)
– 32KBytes (AT32UC3B0256, AT32UC3B0128, AT32UC3B1256 and AT32UC3B1128)
– 16KBytes (AT32UC3B064 and AT32UC3B164)
7.2 Physical Memory Map
The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they
are never remapped in any way, not even in boot. Note that AVR32 UC CPU uses unsegmented
translation, as described in the AVR32UC Technical Architecture Manual. The 32-bit physical
address space is mapped as follows:
Table 7-1. AT32UC3B Physical Memory Map
Device
Embedded
SRAM
Embedded
Flash
USB Data
HSB-PB
Bridge A
HSB-PB
Bridge B
Start Address 0x0000_0000 0x8000_0000 0xD000_0000 0xFFFF_0000 0xFFFE_0000
Size
AT32UC3B0512
AT32UC3B1512
96 Kbytes 512 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes
AT32UC3B0256
AT32UC3B1256
32 Kbytes 256 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes
AT32UC3B0128
AT32UC3B1128
32 Kbytes 128 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes
AT32UC3B064
AT32UC3B164
16 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes