Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 64 (10x10) 32-Bit 60 MHz I/O number 44

Features

• High Performance, Low Power 32-Bit Atmel

AVR

Microcontroller

– Compact Single-cycle RISC Instruction Set Including DSP Instruction Set

– Read-Modify-Write Instructions and Atomic Bit Manipulation

– Performing up to 1.39 DMIPS / MHz

• Up to 83 DMIPS Running at 60 MHz from Flash

• Up to 46 DMIPS Running at 30 MHz from Flash

– Memory Protection Unit

• Multi-hierarchy Bus System

– High-Performance Data Transfers on Separate Buses for Increased Performance

– 7 Peripheral DMA Channels Improves Speed for Peripheral Communication

• Internal High-Speed Flash

– 512K Bytes, 256K Bytes, 128K Bytes, 64K Bytes Versions

– Single Cycle Access up to 30 MHz

– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed

– 4ms Page Programming Time and 8ms Full-Chip Erase Time

– 100,000 Write Cycles, 15-year Data Retention Capability

– Flash Security Locks and User Defined Configuration Area

• Internal High-Speed SRAM, Single-Cycle Access at Full Speed

– 96K Bytes (512KB Flash), 32K Bytes (256KB and 128KB Flash), 16K Bytes (64KB

Flash)

• Interrupt Controller

– Autovectored Low Latency Interrupt Service with Programmable Priority

• System Functions

– Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator

– Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL) allowing

Independant CPU Frequency from USB Frequency

– Watchdog Timer, Real-Time Clock Timer

• Universal Serial Bus (USB)

– Device 2.0 and Embedded Host Low Speed and Full Speed

– Flexible End-Point Configuration and Management with Dedicated DMA Channels

– On-chip Transceivers Including Pull-Ups

– USB Wake Up from Sleep Functionality

• One Three-Channel 16-bit Timer/Counter (TC)

– Three External Clock Inputs, PWM, Capture and Various Counting Capabilities

• One 7-Channel 20-bit Pulse Width Modulation Controller (PWM)

• Three Universal Synchronous/Asynchronous Receiver/Transmitters (USART)

– Independant Baudrate Generator, Support for SPI, IrDA and ISO7816 interfaces

– Support for Hardware Handshaking, RS485 Interfaces and Modem Line

• One Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals

• One Synchronous Serial Protocol Controller

– Supports I

S and Generic Frame-Based Protocols

• One Master/Slave Two-Wire Interface (TWI), 400kbit/s I

C-compatible

• One 8-channel 10-bit Analog-To-Digital Converter, 384ks/s

• 16-bit Stereo Audio Bitstream DAC

– Sample Rate Up to 50 KHz

• QTouch

Library Support

– Capacitive Touch Buttons, Sliders, and Wheels

– QTouch and QMatrix Acquisition

32059L–01/2012

32-bit ATMEL

AVR

Microcontroller

AT32UC3B0512

AT32UC3B0256

AT32UC3B0128

AT32UC3B064

AT32UC3B1512

AT32UC3B1256

AT32UC3B1128

AT32UC3B164

Summary

Summary of content (107 pages)

PAGE 1
Features • High Performance, Low Power 32-Bit Atmel® AVR®Microcontroller • • • • • • • • • • • • • • • – Compact Single-cycle RISC Instruction Set Including DSP Instruction Set – Read-Modify-Write Instructions and Atomic Bit Manipulation – Performing up to 1.
PAGE 2
AT32UC3B • On-Chip Debug System (JTAG interface) – Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace • 64-pin TQFP/QFN (44 GPIO pins), 48-pin TQFP/QFN (28 GPIO pins) • 5V Input Tolerant I/Os, including 4 high-drive pins • Single 3.3V Power Supply or Dual 1.8V-3.
PAGE 3
AT32UC3B 1. Description The AT32UC3B is a complete System-On-Chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 60 MHz. AVR32 UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density and high performance.
PAGE 4
AT32UC3B 2. Overview 2.1 Blockdiagram Figure 2-1. Block diagram NEXUS CLASS 2+ OCD MCKO MDO[5..0] MSEO[1..0] EVTI_N EVTO_N VBUS D+ DID VBOF M USB INTERFACE MEMORY PROTECTION UNIT INSTR INTERFACE DATA INTERFACE M M S HSB HSB-PB BRIDGE B REGISTERS BUS HSB PERIPHERAL DMA CONTROLLER HSB-PB BRIDGE A GENERAL PURPOSE IOs XIN32 XOUT32 XIN0 XOUT0 XIN1 XOUT1 32 KHz OSC CLOCK GENERATOR OSC0 OSC1 PLL0 PLL1 GCLK[3..0] RESET_N A[2..0] B[2..0] CLK[2..
PAGE 5
AT32UC3B 3. Configuration Summary The table below lists all AT32UC3B memory and package configurations: Table 3-1.
PAGE 6
AT32UC3B 4. Package and Pinout 4.1 Package The device pins are multiplexed with peripheral functions as described in the Peripheral Multiplexing on I/O Line section. TQFP64 / QFN64 Pinout 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDDIO PA23 PA22 PA21 PA20 PB07 PA29 PA28 PA19 PA18 PB06 PA17 PA16 PA15 PA14 PA13 Figure 4-1.
PAGE 7
AT32UC3B TQFP48 / QFN48 Pinout 36 35 34 33 32 31 30 29 28 27 26 25 VDDIO PA23 PA22 PA21 PA20 PA19 PA18 PA17 PA16 PA15 PA14 PA13 Figure 4-2. GND DP DM VBUS VDDPLL VDDCORE PA24 PA25 PA26 PA27 RESET_N VDDIO 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 VDDIO PA12 PA11 PA10 PA09 GND VDDCORE VDDIN VDDOUT VDDANA ADVREF GNDANA 12 11 10 9 8 7 6 5 4 3 2 1 PA08 PA07 PA06 PA05 PA04 PA03 VDDCORE PA02 PA01 PA00 TCK GND Note: 4.
PAGE 8
AT32UC3B Table 4-1.
PAGE 9
AT32UC3B Table 4-1. 4.2.2 GPIO Controller Function Multiplexing 55 PB09 GPIO 41 SSC - TX_CLOCK USART1 - RI EIC - SCAN[7] 57 PB10 GPIO 42 SSC - TX_DATA TC - A2 USART0 - RXD 58 PB11 GPIO 43 SSC TX_FRAME_SYNC TC - B2 USART0 - TXD JTAG Port Connections If the JTAG is enabled, the JTAG will take control over a number of pins, irrespective of the I/O Controller configuration. Table 4-2. 64QFP/QFN 4.2.
PAGE 10
AT32UC3B Table 4-4. Oscillator pinout QFP48 pin QFP64 pin Pad Oscillator pin 30 39 PA18 XIN0 41 PA28 XIN1 22 30 PA11 XIN32 31 40 PA19 XOUT0 42 PA29 XOUT1 31 PA12 XOUT32 23 4.3 High Drive Current GPIO Ones of GPIOs can be used to drive twice current than other GPIO capability (see Electrical Characteristics section). Table 4-5. High Drive Current GPIO GPIO Name PA20 PA21 PA22 PA23 5.
PAGE 11
AT32UC3B Table 5-1. Signal Description List (Continued) Signal Name Function Type VDDOUT Voltage Regulator Output Power Output GNDANA Analog Ground Ground GND Ground Ground Active Level Comments 1.65V to 1.
PAGE 12
AT32UC3B Table 5-1.
PAGE 13
AT32UC3B Table 5-1. Signal Description List (Continued) Type Active Level Signal Name Function Comments DCD Data Carrier Detect Only USART1 DSR Data Set Ready Only USART1 DTR Data Terminal Ready Only USART1 RI Ring Indicator Only USART1 RTS Request To Send RXD Receive Data Input TXD Transmit Data Output Output Analog to Digital Converter - ADC AD0 - AD7 Analog input pins Analog input ADVREF Analog positive reference voltage input Analog input 2.6 to 3.
PAGE 14
AT32UC3B 5.2 RESET_N pin The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIO. As the product integrates a power-on reset cell, the RESET_N pin can be left unconnected in case no reset from the system needs to be applied to the product. 5.3 TWI pins When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and inputs with inputs with spike-filtering.
PAGE 15
AT32UC3B Figure 5-1. Power Supply Dual Power Supply Single Power Supply 3.3V 3.3V VDDANA VDDANA VDDIO VDDIO ADVREF ADVREF VDDIN VDDIN 1.8V Regulator VDDOUT VDDOUT 1.8 V VDDCORE VDDCORE VDDPLL VDDPLL 5.6.2 5.6.2.1 1.8V Regulator Voltage Regulator Single Power Supply The AT32UC3B embeds a voltage regulator that converts from 3.3V to 1.8V. The regulator takes its input voltage from VDDIN, and supplies the output voltage on VDDOUT that should be externally connected to the 1.8V domains.
PAGE 16
AT32UC3B Refer to Section 9.3 on page 38 for decoupling capacitors values and regulator characteristics. For decoupling recommendations for VDDIO, VDDANA, VDDCORE and VDDPLL, please refer to the Schematic checklist. 5.6.2.2 Dual Power Supply In case of dual power supply, VDDIN and VDDOUT should be connected to ground to prevent from leakage current. To avoid over consumption during the power up sequence, VDDIO and VDDCORE voltage difference needs to stay in the range given Figure 5-3. Figure 5-3.
PAGE 17
AT32UC3B 6. Processor and Architecture Rev: 1.0.0.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, and MPU is presented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical Reference Manual. 6.
PAGE 18
AT32UC3B The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values from function calls and is used implicitly by some instructions. 6.3 The AVR32UC CPU The AVR32UC CPU targets low- and medium-performance applications, and provides an advanced OCD system, no caches, and a Memory Protection Unit (MPU). Java acceleration hardware is not implemented.
PAGE 19
AT32UC3B OCD interface Reset interface Overview of the AVR32UC CPU Interrupt controller interface Figure 6-1. OCD system Power/ Reset control AVR32UC CPU pipeline MPU 6.3.
PAGE 20
AT32UC3B Figure 6-2. The AVR32UC Pipeline Multiply unit MUL IF ID Pref etch unit Decode unit Regf ile Read A LU LS 6.3.2 Regf ile w rite A LU unit Load-store unit AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is targeted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt contexts.
PAGE 21
AT32UC3B The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Table 6-1. 6.3.6 Instructions with Unaligned Reference Support Instruction Supported alignment ld.d Word st.
PAGE 22
AT32UC3B 6.4 6.4.1 Programming Model Register File Configuration The AVR32UC register file is shown below. Figure 6-3.
PAGE 23
AT32UC3B Figure 6-5. The Status Register Low Halfword Bit 15 Bit 0 - T - - - - - - - - L Q V N Z C Bit name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value Carry Zero Sign Overflow Saturation Lock Reserved Scratch Reserved 6.4.3 6.4.3.1 Processor States Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 6-2 on page 23. Table 6-2. Overview of Execution Modes, their Priorities and Privilege Levels.
PAGE 24
AT32UC3B All interrupt levels are by default disabled when debug state is entered, but they can individually be switched on by the monitor routine by clearing the respective mask bit in the status register. Debug state can be entered as described in the AVR32UC Technical Reference Manual. Debug state is exited by the retd instruction. 6.4.4 System Registers The system registers are placed outside of the virtual memory space, and are only accessible using the privileged mfsr and mtsr instructions.
PAGE 25
AT32UC3B Table 6-3.
PAGE 26
AT32UC3B Table 6-3. 6.
PAGE 27
AT32UC3B The user must also make sure that the system stack is large enough so that any event is able to push the required registers to stack. If the system stack is full, and an event occurs, the system will enter an UNDEFINED state. 6.5.2 Exceptions and Interrupt Requests When an event other than scall or debug request is received by the core, the following actions are performed atomically: 1. The pending event will not be accepted if it is masked.
PAGE 28
AT32UC3B status register. Upon entry into Debug mode, hardware sets the SR[D] bit and jumps to the Debug Exception handler. By default, Debug mode executes in the exception context, but with dedicated Return Address Register and Return Status Register. These dedicated registers remove the need for storing this data to the system stack, thereby improving debuggability.
PAGE 29
AT32UC3B Table 6-4.
PAGE 30
AT32UC3B 6.6 Module Configuration All AT32UC3B parts do not implement the same CPU and Architecture Revision. Table 6-5.
PAGE 31
AT32UC3B 7. Memories 7.
PAGE 32
AT32UC3B 7.3 Peripheral Address Map Table 7-2. Peripheral Address Mapping Address 0xFFFE0000 0xFFFE1000 0xFFFE1400 0xFFFF0000 0xFFFF0800 0xFFFF0C00 0xFFFF0D00 0xFFFF0D30 0xFFFF0D80 0xFFFF1000 0xFFFF1400 0xFFFF1800 0xFFFF1C00 0xFFFF2400 0xFFFF2C00 0xFFFF3000 0xFFFF3400 0xFFFF3800 Peripheral Name USB USB 2.
PAGE 33
AT32UC3B Table 7-2. Peripheral Address Mapping 0xFFFF3C00 ADC 0xFFFF4000 7.4 ABDAC Analog to Digital Converter - ADC Audio Bitstream DAC - ABDAC CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being mapped on the Peripheral Bus. These registers can therefore be reached both by accesses on the Peripheral Bus, and by accesses on the local bus.
PAGE 34
AT32UC3B 8. Boot Sequence This chapter summarizes the boot sequence of the AT32UC3B. The behaviour after power-up is controlled by the Power Manager. For specific details, refer to section Power Manager (PM). 8.1 Starting of clocks After power-up, the device will be held in a reset state by the Power-On Reset circuitry, until the power has stabilized throughout the device. Once the power has stabilized, the device will use the internal RC Oscillator as clock source.
PAGE 35
AT32UC3B 9. Electrical Characteristics 9.1 Absolute Maximum Ratings* Operating Temperature.................................... -40°C to +85°C Storage Temperature ..................................... -60°C to +150°C Voltage on GPIO Pins with respect to Ground for TCK, RESET_N, PA03, PA04, PA05, PA06, PA07, PA08, PA11, PA12, PA18, PA19, PA28, PA29, PA30, PA31 ................................................. -0.3 to 3.
PAGE 36
AT32UC3B 9.2 DC Characteristics The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C, unless otherwise specified and are certified for a junction temperature up to TJ = 100°C. Table 9-1. DC Characteristics Symbol Parameter VVDDCORE DC Supply Core VVDDPLL Conditions Max. Unit 1.65 1.95 V DC Supply PLL 1.65 1.95 V VVDDIO DC Supply Peripheral I/Os 3.0 3.6 V VIL Input Low-level Voltage -0.3 +0.
PAGE 37
AT32UC3B Table 9-1. Symbol CIN DC Characteristics Parameter Input Capacitance Conditions Max. Unit QFP64 7 pF QFP48 7 pF QFN64 7 pF QFN48 7 pF AT32UC3B064 AT32UC3B0128 AT32UC3B0256 AT32UC3B164 AT32UC3B1128 AT32UC3B1256 RPULLUP Pull-up Resistance AT32UC3B0512 AT32UC3B1512 AT32UC3B064 AT32UC3B0128 AT32UC3B0256 AT32UC3B164 AT32UC3B1128 AT32UC3B1256 ISC Static Current AT32UC3B0512 AT32UC3B1512 Min. Typ.
PAGE 38
AT32UC3B 9.3 Regulator Characteristics Table 9-2. Electrical Characteristics Symbol Parameter VVDDIN Supply voltage (input) VVDDOUT Supply voltage (output) IOUT Maximum DC output current VVDDIN = 3.3V ISCR Static Current of internal regulator Low Power mode (stop, deep stop or static) at TA = 25°C Table 9-3. Conditions Min. Typ. Max. Unit 3 3.3 3.6 V 1.70 1.8 1.85 V 100 mA 10 µA Decoupling Requirements Symbol Parameter CIN1 Typ.
PAGE 39
AT32UC3B Table 9-7. BOD Timing Symbol Parameter Conditions TBOD Minimum time with VDDCORE < VBOD to detect power failure Falling VDDCORE from 1.8V to 1.1V 9.4.3 Table 9-8. Min. Typ. Max. Unit 300 800 ns Typ. Max. Unit Reset Sequence Electrical Characteristics Symbol Parameter Conditions Min. VDDRR VDDCORE rise rate to ensure poweron-reset 2.5 VDDFR VDDCORE fall rate to ensure poweron-reset 0.
PAGE 40
AT32UC3B Figure 9-1. VDDCORE MCU Cold Start-Up RESET_N tied to VDDIN VPOR- VPOR+ VRESTART RESET_N Internal POR Reset TPOR TRST TSSU1 Internal MCU Reset Figure 9-2. VDDCORE MCU Cold Start-Up RESET_N Externally Driven VPOR- VPOR+ VRESTART RESET_N Internal POR Reset TPOR TRST TSSU1 Internal MCU Reset Figure 9-3.
PAGE 41
AT32UC3B Therefore VDDCORE rise rate (VDDRR) must be equal or superior to 2.5V/ms and VDDIO must reach VDDIO mini value before 500 us (< TRST + TSSU1) after VDDCORE has reached VPOR+ min value. Figure 9-4. Dual Supply Configuration V D D IO m in V p o r+ m in VDDCORE 2.5 VD V/ m DRR sm in i m um V D D IO <500us TSSU1 TRST In te rn a l POR (a c tiv e lo w ) F irs t in s tru c tio n fe tc h e d in fla sh 9.4.4 Table 9-9.
PAGE 42
AT32UC3B 9.5 Power Consumption The values in Table 9-10, Table 9-11 on page 43 and Table 9-12 on page 44 are measured values of power consumption with operating conditions as follows: •VDDIO = VDDANA = 3.3V •VDDCORE = VDDPLL = 1.8V •TA = 25°C, TA = 85°C •I/Os are configured in input, pull-up enabled. Figure 9-5. Measurement Setup VDDANA VDDIO Amp0 VDDIN Internal Voltage Regulator VDDOUT Amp1 VDDCORE VDDPLL The following tables represent the power consumption measured on the power supplies.
PAGE 43
AT32UC3B 9.5.1 Power Consumtion for Different Sleep Modes Table 9-10. Mode Power Consumption for Different Sleep Modes for AT32UC3B064, AT32UC3B0128, AT32UC3B0256, AT32UC3B164, AT32UC3B1128, AT32UC3B1256 Conditions Typ. Unit 0.3xf(MHz)+0.443 mA/MHz Same conditions at 60 MHz 18.5 mA See Active mode conditions 0.117xf(MHz)+0.28 mA/MHz Same conditions at 60 MHz 7.3 mA See Active mode conditions 0.058xf(MHz)+0.115 mA/MHz Same conditions at 60 MHz 3.6 mA See Active mode conditions 0.
PAGE 44
AT32UC3B Table 9-11. Mode Power Consumption for Different Sleep Modes for AT32UC3B0512, AT32UC3B1512 Conditions Typ. Unit See Active mode conditions 0.0723xf(MHz)+0.15 6 mA/MHz Same conditions at 60 MHz 4.5 mA See Active mode conditions 0.0537xf(MHz)+0.16 6 mA/MHz Same conditions at 60 MHz 3.4 mA Stop - CPU running in sleep mode - XIN0, Xin1 and XIN32 are stopped. - All peripheral clocks are desactived.
PAGE 45
AT32UC3B 9.6 System Clock Characteristics These parameters are given in the following conditions: • VDDCORE = 1.8V • Ambient Temperature = 25°C 9.6.1 CPU/HSB Clock Characteristics Table 9-13. Core Clock Waveform Parameters Symbol Parameter 1/(tCPCPU) CPU Clock Frequency tCPCPU CPU Clock Period 9.6.2 Min. Typ. Max. Unit 60 MHz 16.6 ns PBA Clock Characteristics Table 9-14. PBA Clock Waveform Parameters Symbol Parameter 1/(tCPPBA) PBA Clock Frequency tCPPBA PBA Clock Period 9.6.
PAGE 46
AT32UC3B 9.7 Oscillator Characteristics The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C and worst case of power supply, unless otherwise specified. 9.7.1 Slow Clock RC Oscillator Table 9-16. Symbol RC Oscillator Frequency Parameter Conditions Min. Calibration point: TA = 85°C FRC RC Oscillator Frequency 9.7.2 TA = 25°C Typ. Max. Unit 115.2 116 KHz 112 KHz KHz TA = -40°C 105 108 Conditions Min. Typ. 32 KHz Oscillator Table 9-17.
PAGE 47
AT32UC3B 9.7.3 Main Oscillators Table 9-18. Main Oscillators Characteristics Symbol Parameter 1/(tCPMAIN) Oscillator Frequency CL1, CL2 Internal Load Capacitance (CL1 = CL2) ESR Crystal Equivalent Series Resistance Conditions Min. Typ. External clock on XIN Crystal 0.4 Max. Unit 50 MHz 20 MHz 7 Duty Cycle 40 50 f = 400 KHz f = 8 MHz f = 16 MHz f = 20 MHz pF 75 Ω 60 % 25 4 1.4 1 ms tST Startup Time tCH XIN Clock High Half-period 0.4 tCP 0.
PAGE 48
AT32UC3B 9.8 ADC Characteristics Table 9-20. Channel Conversion Time and ADC Clock Parameter Conditions ADC Clock Frequency Max. Unit 10-bit resolution mode 5 MHz ADC Clock Frequency 8-bit resolution mode 8 MHz Startup Time Return from Idle Mode 20 µs Track and Hold Acquisition Time Min. Typ. 600 ns Track and Hold Input Resistor 350 Ω Track and Hold Capacitor 12 pF Conversion Time Throughput Rate Notes: ADC Clock = 5 MHz 2 ADC Clock = 8 MHz 1.
PAGE 49
AT32UC3B Table 9-23. Transfer Characteristics in 8-bit Mode Parameter Conditions Differential Non-linearity Min. Typ. Max. Unit ADC Clock = 5 MHz 0.3 0.5 LSB ADC Clock = 8 MHz 0.5 1.0 LSB Offset Error ADC Clock = 5 MHz -0.5 0.5 LSB Gain Error ADC Clock = 5 MHz -0.5 0.5 LSB Max. Unit Table 9-24. Transfer Characteristics in 10-bit Mode Parameter Conditions Min.
PAGE 50
AT32UC3B 9.9 USB Transceiver Characteristics 9.9.1 Electrical Characteristics Table 9-25. Electrical Parameters Symbol Parameter Conditions REXT Recommended external USB series resistor In series with each USB pin with ±5% Min. Typ. 39 Max. Unit Ω The USB on-chip buffers comply with the Universal Serial Bus (USB) v2.0 standard. All AC parameters related to these buffers can be found within the USB 2.0 electrical specifications.
PAGE 51
AT32UC3B 9.10 JTAG Characteristics 9.10.1 JTAG Timing Figure 9-6. JTAG Interface Signals JTAG2 TCK JTAG0 JTAG1 TMS/TDI JTAG3 JTAG4 JTAG7 JTAG8 TDO JTAG5 JTAG6 Boundary Scan Inputs Boundary Scan Outputs JTAG9 JTAG10 Table 9-26. JTAG Timings(1) Symbol Parameter Conditions JTAG0 TCK Low Half-period 23.2 ns JTAG1 TCK High Half-period 8.8 ns JTAG2 TCK Period 32.0 ns JTAG3 TDI, TMS Setup before TCK High 3.9 ns JTAG4 TDI, TMS Hold after TCK High 0.
PAGE 52
AT32UC3B 9.11 SPI Characteristics Figure 9-7. SPI Master mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1) SPCK SPI0 SPI1 MISO SPI2 MOSI Figure 9-8. SPI Master mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0) SPCK SPI3 SPI4 MISO SPI5 MOSI Figure 9-9.
PAGE 53
AT32UC3B Figure 9-10. SPI Slave mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1) SPCK SPI9 MISO SPI10 SPI11 MOSI Table 9-27. SPI Timings Symbol Parameter SPI0 MISO Setup time before SPCK rises (master) 3.3V domain(1) 22 + (tCPMCK)/2(2) ns SPI1 MISO Hold time after SPCK rises (master) 3.3V domain(1) 0 ns SPI2 SPCK rising to MOSI Delay (master) 3.3V domain(1) SPI3 MISO Setup time before SPCK falls (master) 3.
PAGE 54
AT32UC3B 9.12 Flash Memory Characteristics The following table gives the device maximum operating frequency depending on the field FWS of the Flash FSR register. This field defines the number of wait states required to access the Flash Memory. Flash operating frequency equals the CPU/HSB frequency. Table 9-28. Flash Operating Frequency Symbol Parameter FFOP Flash Operating Frequency Table 9-29. Conditions Min. Typ. Max. Unit FWS = 0 33 MHz FWS = 1 60 MHz Max.
PAGE 55
AT32UC3B 10. Mechanical Characteristics 10.1 10.1.1 Thermal Considerations Thermal Data Table 10-1 summarizes the thermal resistance data depending on the package. Table 10-1. 10.1.2 Thermal Resistance Data Symbol Parameter Condition Package Typ θJA Junction-to-ambient thermal resistance Still Air TQFP64 49.6 θJC Junction-to-case thermal resistance TQFP64 13.5 θJA Junction-to-ambient thermal resistance TQFP48 51.1 θJC Junction-to-case thermal resistance TQFP48 13.
PAGE 56
AT32UC3B 10.2 Package Drawings Figure 10-1. TQFP-64 package drawing Table 10-2. Device and Package Maximum Weight Weight Table 10-3. 300 mg Package Characteristics Moisture Sensitivity Level Table 10-4.
PAGE 57
AT32UC3B Figure 10-2. TQFP-48 package drawing Table 10-5. Device and Package Maximum Weight Weight Table 10-6. 100 mg Package Characteristics Moisture Sensitivity Level Table 10-7.
PAGE 58
AT32UC3B Figure 10-3. QFN-64 package drawing Table 10-8. Device and Package Maximum Weight Weight Table 10-9. 200 mg Package Characteristics Moisture Sensitivity Level Jedec J-STD-20D-MSL3 Table 10-10.
PAGE 59
AT32UC3B Figure 10-4. QFN-48 package drawing Table 10-11. Device and Package Maximum Weight Weight 100 mg Table 10-12. Package Characteristics Moisture Sensitivity Level Jedec J-STD-20D-MSL3 Table 10-13.
PAGE 60
AT32UC3B 10.3 Soldering Profile Table 10-14 gives the recommended soldering profile from J-STD-20. Table 10-14. Soldering Profile Profile Feature Green Package Average Ramp-up Rate (217°C to Peak) 3°C/s Preheat Temperature 175°C ±25°C Min. 150°C, Max. 200°C Temperature Maintained Above 217°C 60-150s Time within 5⋅C of Actual Peak Temperature 30s Peak Temperature Range 260°C Ramp-down Rate 6°C/s Time 25⋅C to Peak Temperature Max.
PAGE 61
AT32UC3B 11.
PAGE 62
AT32UC3B 12. Errata 12.1 12.1.1 AT32UC3B0512, AT32UC3B1512 Rev D - PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 2. PWN counter restarts at 0x0001 The PWM counter restarts at 0x0001 and not 0x0000 as specified.
PAGE 63
AT32UC3B 7. SPI Glitch on RXREADY flag in slave mode when enabling the SPI or during the first transfer In slave mode, the SPI can generate a false RXREADY signal during enabling of the SPI or during the first transfer. Fix/Workaround 1. Set slave mode, set required CPOL/CPHA. 2. Enable SPI. 3. Set the polarity CPOL of the line in the opposite value of the required one. 4. Set the polarity CPOL to the required one. 5. Read the RXHOLDING register.
PAGE 64
AT32UC3B will not be turned off. This will result in a significantly higher power consumption during the sleep mode. Fix/Workaround Before going to sleep modes where the system RC oscillator is stopped, make sure that the factor between the CPU/HSB and PBx frequencies is less than or equal to 4. 15. Increased Power Consumption in VDDIO in sleep modes If the OSC0 is enabled in crystal mode when entering a sleep mode where the OSC0 is disabled, this will lead to an increased power consumption in VDDIO.
PAGE 65
AT32UC3B 20. USB 21. UPCFGn.INTFRQ is irrelevant for isochronous pipe As a consequence, isochronous IN and OUT tokens are sent every 1ms (Full Speed), or every 125uS (High Speed). Fix/Workaround For higher polling time, the software must freeze the pipe for the desired period in order to prevent any "extra" token. - ADC 1. Sleep Mode activation needs additional A to D conversion If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode before after the next AD conversion.
PAGE 66
AT32UC3B 7. TC 8. Channel chaining skips first pulse for upper channel When chaining two channels using the Block Mode Register, the first pulse of the clock between the channels is skipped. Fix/Workaround Configure the lower channel with RA = 0x1 and RC = 0x2 to produce a dummy clock cycle for the upper channel. After the dummy cycle has been generated, indicated by the SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real values. - Processor and Architecture 1.
PAGE 67
AT32UC3B the receive buffer is full. In the interrupt handler code, write a one to the RTSDIS bit in the USART Control Register (CR). This will drive the RTS output high. After the next DMA transfer is started and a receive buffer is available, write a one to the RTSEN bit in the USART CR so that RTS will be driven low. 8.
PAGE 68
AT32UC3B 12.1.2 Rev C - PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 2. PWN counter restarts at 0x0001 The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first PWM period has one more clock cycle.
PAGE 69
AT32UC3B 8. SPI disable does not work in SLAVE mode SPI disable does not work in SLAVE mode. Fix/Workaround Read the last received data, then perform a software reset by writing a one to the Software Reset bit in the Control Register (CR.SWRST). 9. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0 When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI module will not start a data transfer. Fix/Workaround Disable mode fault detection by writing a one to MR.MODFDIS. 10.
PAGE 70
AT32UC3B 16. Increased Power Consumption in VDDIO in sleep modes If the OSC0 is enabled in crystal mode when entering a sleep mode where the OSC0 is disabled, this will lead to an increased power consumption in VDDIO. Fix/Workaround Disable the OSC0 through the Power Manager (PM) before going to any sleep mode where the OSC0 is disabled, or pull down or up XIN0 and XOUT0 with 1Mohm resistor. 17. SSC 18. Additional delay on TD output A delay from 2 to 3 system clock cycles is added to TD output when: TCMR.
PAGE 71
AT32UC3B - PDCA 1. Wrong PDCA behavior when using two PDCA channels with the same PID Wrong PDCA behavior when using two PDCA channels with the same PID. Fix/Workaround The same PID should not be assigned to more than one channel. 2.
PAGE 72
AT32UC3B - Processor and Architecture 1. LDM instruction with PC in the register list and without ++ increments Rp For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the increment of the pointer is done in parallel with the testing of R12. Fix/Workaround None. 2.
PAGE 73
AT32UC3B fer is started and a receive buffer is available, write a one to the RTSEN bit in the USART CR so that RTS will be driven low. 4. Corruption after receiving too many bits in SPI slave mode If the USART is in SPI slave mode and receives too much data bits (ex: 9bitsinstead of 8 bits) by the SPI master, an error occurs. After that, the next reception may be corrupted even if the frame is correct and the USART has been disabled, reset by a soft reset and reenabled. Fix/Workaround None. 5.
PAGE 74
AT32UC3B 12.2 AT32UC3B0256, AT32UC3B0128, AT32UC3B064, AT32UC3B1256, AT32UC3B1128, AT32UC3B164 All industrial parts labelled with -UES (for engineering samples) are revision B parts. 12.2.1 Rev I, J, K - PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 2.
PAGE 75
AT32UC3B 3. Set the polarity CPOL of the line in the opposite value of the required one. 4. Set the polarity CPOL to the required one. 5. Read the RXHOLDING register. Transfers can now begin and RXREADY will now behave as expected. 8. SPI disable does not work in SLAVE mode SPI disable does not work in SLAVE mode. Fix/Workaround Read the last received data, then perform a software reset by writing a one to the Software Reset bit in the Control Register (CR.SWRST). 9. SPI data transfer hangs with CSR0.
PAGE 76
AT32UC3B 14. SSC 15. Additional delay on TD output A delay from 2 to 3 system clock cycles is added to TD output when: TCMR.START = Receive Start, TCMR.STTDLY = more than ZERO, RCMR.START = Start on falling edge / Start on Rising edge / Start on any edge, RFMR.FSOS = None (input). Fix/Workaround None. 16. TF output is not correct TF output is not correct (at least emitted one serial clock cycle later than expected) when: TFMR.FSOS = Driven Low during data transfer/ Driven High during data transfer TCMR.
PAGE 77
AT32UC3B 2. Transfer error will stall a transmit peripheral handshake interface If a transfer error is encountered on a channel transmitting to a peripheral, the peripheral handshake of the active channel will stall and the PDCA will not do any more transfers on the affected peripheral handshake interface. Fix/Workaround Disable and then enable the peripheral after the transfer error. 3. TWI 4.
PAGE 78
AT32UC3B - Processor and Architecture 1. LDM instruction with PC in the register list and without ++ increments Rp For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the increment of the pointer is done in parallel with the testing of R12. Fix/Workaround None. 2.
PAGE 79
AT32UC3B even if the frame is correct and the USART has been disabled, reset by a soft reset and reenabled. Fix/Workaround None. 9. USART slave synchronous mode external clock must be at least 9 times lower in frequency than CLK_USART When the USART is operating in slave synchronous mode with an external clock, the frequency of the signal provided on CLK must be at least 9 times lower than CLK_USART.
PAGE 80
AT32UC3B 12.2.2 Rev. G - PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 2. PWN counter restarts at 0x0001 The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first PWM period has one more clock cycle.
PAGE 81
AT32UC3B 8. SPI disable does not work in SLAVE mode SPI disable does not work in SLAVE mode. Fix/Workaround Read the last received data, then perform a software reset by writing a one to the Software Reset bit in the Control Register (CR.SWRST). 9. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0 When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI module will not start a data transfer. Fix/Workaround Disable mode fault detection by writing a one to MR.MODFDIS. 10.
PAGE 82
AT32UC3B 15. SSC 16. Additional delay on TD output A delay from 2 to 3 system clock cycles is added to TD output when: TCMR.START = Receive Start, TCMR.STTDLY = more than ZERO, RCMR.START = Start on falling edge / Start on Rising edge / Start on any edge, RFMR.FSOS = None (input). Fix/Workaround None. 17. TF output is not correct TF output is not correct (at least emitted one serial clock cycle later than expected) when: TFMR.FSOS = Driven Low during data transfer/ Driven High during data transfer TCMR.
PAGE 83
AT32UC3B 2. Transfer error will stall a transmit peripheral handshake interface If a transfer error is encountered on a channel transmitting to a peripheral, the peripheral handshake of the active channel will stall and the PDCA will not do any more transfers on the affected peripheral handshake interface. Fix/Workaround Disable and then enable the peripheral after the transfer error. 3. TWI 4.
PAGE 84
AT32UC3B - OCD 1. The auxiliary trace does not work for CPU/HSB speed higher than 50MHz The auxiliary trace does not work for CPU/HSB speed higher than 50MHz. Fix/Workaround Do not use the auxiliary trace for CPU/HSB speed higher than 50MHz. - Processor and Architecture 1. LDM instruction with PC in the register list and without ++ increments Rp For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is always updated.
PAGE 85
AT32UC3B 8. The RTS output does not function correctly in hardware handshaking mode The RTS signal is not generated properly when the USART receives data in hardware handshaking mode. When the Peripheral DMA receive buffer becomes full, the RTS output should go high, but it will stay low. Fix/Workaround Do not use the hardware handshaking mode of the USART. If it is necessary to drive the RTS output high when the Peripheral DMA receive buffer becomes full, use the normal mode of the USART.
PAGE 86
AT32UC3B - DSP Operations 1. Hardware breakpoints may corrupt MAC results Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC instruction. Fix/Workaround Place breakpoints on earlier or later instructions.
PAGE 87
AT32UC3B 12.2.3 Rev. F - PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 2. PWN counter restarts at 0x0001 The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first PWM period has one more clock cycle.
PAGE 88
AT32UC3B 8. SPI disable does not work in SLAVE mode SPI disable does not work in SLAVE mode. Fix/Workaround Read the last received data, then perform a software reset by writing a one to the Software Reset bit in the Control Register (CR.SWRST). 9. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0 When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI module will not start a data transfer. Fix/Workaround Disable mode fault detection by writing a one to MR.MODFDIS. 10.
PAGE 89
AT32UC3B 15. SSC 16. Additional delay on TD output A delay from 2 to 3 system clock cycles is added to TD output when: TCMR.START = Receive Start, TCMR.STTDLY = more than ZERO, RCMR.START = Start on falling edge / Start on Rising edge / Start on any edge, RFMR.FSOS = None (input). Fix/Workaround None. 17. TF output is not correct TF output is not correct (at least emitted one serial clock cycle later than expected) when: TFMR.FSOS = Driven Low during data transfer/ Driven High during data transfer TCMR.
PAGE 90
AT32UC3B 2. Transfer error will stall a transmit peripheral handshake interface If a transfer error is encountered on a channel transmitting to a peripheral, the peripheral handshake of the active channel will stall and the PDCA will not do any more transfers on the affected peripheral handshake interface. Fix/Workaround Disable and then enable the peripheral after the transfer error. 3. TWI 4.
PAGE 91
AT32UC3B SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real values. - OCD 1. The auxiliary trace does not work for CPU/HSB speed higher than 50MHz The auxiliary trace does not work for CPU/HSB speed higher than 50MHz. Fix/Workaround Do not use the auxiliary trace for CPU/HSB speed higher than 50MHz. - Processor and Architecture 1.
PAGE 92
AT32UC3B 7. ISO7816 Mode T1: RX impossible after any TX RX impossible after any TX. Fix/Workaround SOFT_RESET on RX+ Config US_MR + Config_US_CR. 8. The RTS output does not function correctly in hardware handshaking mode The RTS signal is not generated properly when the USART receives data in hardware handshaking mode. When the Peripheral DMA receive buffer becomes full, the RTS output should go high, but it will stay low. Fix/Workaround Do not use the hardware handshaking mode of the USART.
PAGE 93
AT32UC3B and filling the write buffer with all one (FFh) will leave the current flash content unchanged. It is then safe to read and fetch code from the flash. - DSP Operations 1. Hardware breakpoints may corrupt MAC results Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC instruction. Fix/Workaround Place breakpoints on earlier or later instructions.
PAGE 94
AT32UC3B 12.2.4 Rev. B - PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 2. PWN counter restarts at 0x0001 The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first PWM period has one more clock cycle.
PAGE 95
AT32UC3B 8. SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and NCPHA=0 When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one (CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0, then an additional pulse will be generated on SCK. Fix/Workaround When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1 if CSRn.CPOL=1 and CSRn.NCPHA=0. 9.
PAGE 96
AT32UC3B - SSC 1. SSC does not trigger RF when data is low The SSC cannot transmit or receive data when CKS = CKDIV and CKO = none, in TCMR or RCMR respectively. Fix/Workaround Set CKO to a value that is not "none" and bypass the output of the TK/RK pin with the GPIO. - USB 1. USB No end of host reset signaled upon disconnection In host mode, in case of an unexpected device disconnection whereas a usb reset is being sent by the usb controller, the UHCON.
PAGE 97
AT32UC3B - USART 1. USART Manchester Encoder Not Working Manchester encoding/decoding is not working. Fix/Workaround Do not use manchester encoding. 2. USART RXBREAK problem when no timeguard In asynchronous mode the RXBREAK flag is not correctly handled when the timeguard is 0 and the break character is located just after the stop bit. Fix/Workaround If the NBSTOP is 1, timeguard should be different from 0. 3.
PAGE 98
AT32UC3B 2. The command Quick Page Read User Page(QPRUP) is not functional The command Quick Page Read User Page(QPRUP) is not functional. Fix/Workaround None. 3. PAGEN Semantic Field for Program GP Fuse Byte is WriteData[7:0], ByteAddress[1:0] on revision B instead of WriteData[7:0], ByteAddress[2:0] PAGEN Semantic Field for Program GP Fuse Byte is WriteData[7:0], ByteAddress[1:0] on revision B instead of WriteData[7:0], ByteAddress[2:0]. Fix/Workaround None. 4.
PAGE 99
AT32UC3B - OCD 1. Stalled memory access instruction writeback fails if followed by a HW breakpoint Consider the following assembly code sequence: A B If a hardware breakpoint is placed on instruction B, and instruction A is a memory access instruction, register file updates from instruction A can be discarded. Fix/Workaround Do not place hardware breakpoints, use software breakpoints instead.
PAGE 100
AT32UC3B Figure 12-1. Timer/Counter clock connections on RevB Source Name Connection Internal TIMER_CLOCK1 32KHz Oscillator TIMER_CLOCK2 PBA Clock / 4 TIMER_CLOCK3 PBA Clock / 8 TIMER_CLOCK4 PBA Clock / 16 TIMER_CLOCK5 PBA Clock / 32 External XC0 XC1 XC2 7. Spurious interrupt may corrupt core SR mode to exception If the rules listed in the chapter `Masking interrupt requests in peripheral modules' of the AVR32UC Technical Reference Manual are not followed, a spurious interrupt may occur.
PAGE 101
AT32UC3B it is done atomically. Even if this step is described in general as not safe in the UC technical reference guide, it is safe in this very specific case. 2. Execute the RETE instruction.
PAGE 102
AT32UC3B 13. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 13.1 Rev. L– 01/2012 1. 13.2 13.3 13.4 13.5 Updated Mechanical Characteristics section. Rev. K– 02/2011 1. Updated USB section. 2. Updated Configuration Summary section. 3. Updated Electrical Characteristics section. 4. Updated Errata section. Rev. J– 12/2010 1.
PAGE 103
AT32UC3B 13.6 13.7 Rev. G – 06/2009 1. Open Drain Mode removed from GPIO section. 2 Updated Errata section. Rev. F – 04/2008 1. 13.8 Rev. E – 12/2007 1. 13.9 Updated Errata section. Updated Memory Protection section. Rev. D – 11/2007 1. Updated Processor Architecture section. 2. Updated Electrical Characteristics section. 13.10 Rev. C – 10/2007 1. Updated Features sections. 2. Updated block diagram with local bus figure 3. Add schematic for HMatrix master/slave connection. 4.
PAGE 104
AT32UC3B 13.12 Rev. A – 05/2007 1. Initial revision.
PAGE 105
AT32UC3B Table of Contents 1 Description ............................................................................................... 3 2 Overview ................................................................................................... 4 2.1 Blockdiagram .....................................................................................................4 3 Configuration Summary .......................................................................... 5 4 Package and Pinout ..........
PAGE 106
AT32UC3B 9.2 DC Characteristics ...........................................................................................36 9.3 Regulator Characteristics ................................................................................38 9.4 Analog Characteristics .....................................................................................38 9.5 Power Consumption ........................................................................................42 9.6 System Clock Characteristics ...
PAGE 107
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: (+1)(408) 441-0311 Fax: (+1)(408) 487-2600 www.atmel.com Atmel Asia Limited Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan 16F, Shin Osaki Kangyo Bldg.