Datasheet

54
32072SH–AVR32–10/2012
AT32UC3A3
7.9 ADC Characteristics
Table 7-22. Channel Conversion Time and ADC Clock
Parameter Conditions Min. Typ. Max. Unit
ADC Clock Frequency
10-bit resolution mode 5 MHz
8-bit resolution mode 8 MHz
Startup Time Return from Idle Mode 20 µs
Track and Hold Acquisition Time 600 ns
Conversion Time
ADC Clock = 5 MHz 2 µs
ADC Clock = 8 MHz 1.25 µs
Throughput Rate
ADC Clock = 5 MHz 384
(1)
1. Corresponds to 13 clock cycles: 3 clock cycles for track and hold acquisition time and 10 clock cycles for conversion.
kSPS
ADC Clock = 8 MHz 533
(2)
2. Corresponds to 15 clock cycles: 5 clock cycles for track and hold acquisition time and 10 clock cycles for conversion.
kSPS
Table 7-23. ADC Power Consumption
Parameter Conditions Min. Typ. Max. Unit
Current Consumption on VDDANA
(1)
1. Including internal reference input current
On 13 samples with ADC clock = 5 MHz 1.25 mA
Table 7-24. Analog Inputs
Parameter Conditions Min. Typ. Max. Unit
Input Voltage Range 0 VDDANA V
Input Leakage Current 1µA
Input Capacitance 7pF
Input Resistance 350 850 Ohm
Table 7-25. Transfer Characteristics in 8-bit mode
Parameter Conditions Min. Typ. Max. Unit
Resolution 8Bit
Absolute Accuracy
ADC Clock = 5 MHz 0.8 LSB
ADC Clock = 8 MHz 1.5 LSB
Integral Non-linearity
ADC Clock = 5 MHz 0.35 0.5 LSB
ADC Clock = 8 MHz 0.5 1.5 LSB
Differential Non-linearity
ADC Clock = 5 MHz 0.3 0.5 LSB
ADC Clock = 8 MHz 0.5 1.5 LSB
Offset Error ADC Clock = 5 MHz -1.5 1.5 LSB
Gain Error ADC Clock = 5 MHz -0.5 0.5 LSB