Datasheet

937
32072H–AVR32–10/2012
AT32UC3A3
35.4.5.1 Power Management
When an instruction that accesses the SAB is loaded in the instruction register, before entering
a sleep mode, the system clocks are not switched off to allow debugging in sleep modes. This
can lead to a program behaving differently when debugging.
35.4.5.2 Clocks
The JTAG Interface uses the external TCK pin as clock source. This clock must be provided by
the JTAG master.
Instructions that use the SAB bus requires the internal main clock to be running.
35.4.6 JTAG Interface
The JTAG Interface is accessed through the dedicated JTAG pins shown in Table 35-6 on page
936. The TMS control line navigates the TAP controller, as shown in Figure 35-5 on page 938.
The TAP controller manages the serial access to the JTAG Instruction and Data registers. Data
is scanned into the selected instruction or data register on TDI, and out of the register on TDO,
in the Shift-IR and Shift-DR states, respectively. The LSB is shifted in and out first. TDO is high-
Z in other states than Shift-IR and Shift-DR.
The device implements a 5-bit Instruction Register (IR). A number of public JTAG instructions
defined by the JTAG standard are supported, as described in Section 35.5.2, as well as a num-
ber of 32-bit AVR-specific private JTAG instructions described in Section 35.5.3. Each
instruction selects a specific data register for the Shift-DR path, as described for each
instruction.