Datasheet

929
32072H–AVR32–10/2012
AT32UC3A3
35.3.3 Block Diagram
Figure 35-1.
On-Chip Debug Block Diagram
35.3.4 JTAG-based Debug Features
A debugger can control all OCD features by writing OCD registers over the JTAG interface.
Many of these do not depend on output on the AUX port, allowing a JTAG-based debugger to be
used.
A JTAG-based debugger should connect to the device through a standard 10-pin IDC connector
as described in the AVR32UC Technical Reference Manual.
On-Chip Debug
JTAG
Debug PC
Debug
Instruction
CPU
Breakpoints
Program
Trace
Data Trace
Ownership
Trace
WatchpointsTransmit Queue
AUX
JTAG
Internal
SRAM
S
e
r
v
i
c
e
A
c
c
e
s
s
B
u
s
Memory
Service
Unit
HSB Bus Matrix
Memories and
peripherals