Datasheet

895
32072H–AVR32–10/2012
AT32UC3A3
Figure 33-3. DMA Mode when MR.LOD is zero
• when MR.LOD is one
The user must first wait for the DMA Controller Interrupt, then for ISR.DATRDY to ensure that
the encryption/decryption is completed.
In this case, no receive buffers are required.
The output data is only available in ODATAnR registers.
Figure 33-4. DMA Mode when MR.LOD is one
Following table summarizes the different cases.
Note: 1. Depending on the mode, there are other ways of clearing the DATRDY.ISR bit. See the Interrupt Status Register (ISR)
definition.
Warning: In DMA mode, reading to the ODATAnR registers before the last data transfer may lead to unpredictable results.
DMA Controller Interrupt
Multiple encryption or decryption processes
Enable DMA Controller Channels (Receive and Transmit Channels)
Enable DMA Controller Channels (only Transmit Channel)
ISR.DATRDY
Multiple Encryption or Decryption Processes
DMA Controller Interrupt
Table 33-3. Last Output Mode Behavior versus Start Modes
Manual and Automatic Modes DMA Mode
MR.LOD = 0 MR.LOD = 1 MR.LOD = 0 MR.LOD = 1
ISR.DATRDY bit Clearing
Condition
(1)
At least one ODATAnR
register must be read
At least one IDATAnR
register must be written
Not used
Managed by the DMA
Controller
Encrypted/Decrypted
Data Result Location
In ODATAnR registers In ODATAnR registers
At the address
specified in the
configuration of
DMA Controller
In ODATAnR registers
End of
Encryption/Decryption
ISR.DATRDY ISR.DATRDY
DMA Controller
Interrupt
DMA Controller
Interrupt then
DATRDY.ISR