Datasheet

882
32072H–AVR32–10/2012
AT32UC3A3
32.7.4 System register
Name :
SYS
Access Type : Read/Write
Offset : 0x0C
Reset Value : 0x00004015
•
CLKDIV : Clock Division.
Write this field to change SCLK frequency = CLK_MSI / (2*(CLKDIV+1)).
•
RST : Reset. When RST is written, internal synchronous reset is performed.
0 : This bit is cleared to 0 after the internal reset is completed.
1 : Writing a 1 starts reset operation.
•
SRAC : Serial Access Mode. The SRAC cannot be changed during protocol execution.
0 : Write this bit to 0 to set parallel mode.
1 : Write this bit to 1 to set serial mode.
•
NOCRC : No CRC computation.
0 : Write 0 to enable CRC output. During read protocol, the CRC check is performed as usual regardless of NOCRC.
1 : Write 1 to disable CRC output. When NOCRC=1, the write protocol is executed without adding the CRC data.
•
FCLR : FIFO clear.
Write 1 to initialize FIFO data. This bit is cleared after the FIFO is initialized.
•
FDIR : FIFO direction.
0 : Write 0 to set the FIFO direction to transmit.
1 : Write 1 to set the FIFO direction to receive.
•
REI : Rising Edge Input. When setting parallel mode, set REI=0. This setting cannot be changed during protocol execution.
0 : Write 0 to sample data at the falling edge of SCLK.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
CLKDIV
15 14 13 12 11 10 9 8
RST SRAC - NOCRC - - FCLR FDIR
76543210
- - - REI REO BSY