Datasheet

876
32072H–AVR32–10/2012
AT32UC3A3
the interrupt source, even if the interrupt is masked, can be read in ISR.
DRQ interrupt request is cleared by reading (reception) or writing (transmission) FIFO, other
interrupt requests are cleared by writing 1 to the corresponding bit in Interrupt Status Clear Reg-
ister (ISCR).
32.6.6 OCD mode
There is no OCD mode for MSI.
32.7 User Interface
Table 32-2. MSI Register Memory Map
Offset Register Name Access Reset State
0x0000 Command register CMD Read/Write 0x00000000
0x0004 Data register DAT Read/Write 0x4C004C00
0x0008 Status register SR Read Only 0x00001020
0x000C System register SYS Read/Write 0x00004015
0x0010 Interrupt Status register ISR Read Only 0x00000000
0x0014 Interrupt Status Clear register ISCR Write Only 0x00000000
0x0018 Interrupt Enable register IER Write Only 0x00000000
0x001C Interrupt Disable register IDR Write Only 0x00000000
0x0020 Interrupt Mask register IMR Read Only 0x00000000
0x0024 Version register VERSION Read Only 0x00000210