Datasheet

853
32072H–AVR32–10/2012
AT32UC3A3
31.7.8 Completion Signal Time-out Register
Name:
CSTOR
Access Type: Read-write
Offset: 0x01C
Reset Value: 0x00000000
These two fields determines the maximum number of CLK_MCI cycles that the MCI waits between two data block transfers. Its
value is calculated by (CSTOCYC x Multiplier).
These two fields also determine the maximum number of CLK_MCI cycles that the MCI waits between the end of the data
transfer and the assertion of the completion signal. The data transfer comprises data phase and the optional busy phase. If a
non-DATA ATA command is issued, the MCI starts waiting immediately after the end of the response until the completion signal.
If the data time-out defined by CSTOCYC and CSTOMUL has been exceeded, the Completion Signal Time-out Error bit in the
SR register (SR.CSTOE) is set.
• CSTOMUL: Completion Signal Time-out Multiplier
Multiplier is defined by CSTOMUL as shown in the following table:
• CSTOCYC: Completion Signal Time-out Cycle Number
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- CSTOMUL CSTOCYC
CSTOMUL Multiplier
01
116
2128
3256
4 1024
5 4096
6 65536
7 1048576