Datasheet

849

32072H–AVR32–10/2012

AT32UC3A3

31.7.6 Command Register

Name:

CMDR

Access Type: Write-only

Offset: 0x014

Reset Value: 0x00000000

This register is write-protected while SR.CMDRDY is zero. If an interrupt command is sent, this register is only writable by an

interrupt response (SPCMD field). This means that the current command execution cannot be interrupted or modified.

• BOOT_ACK: Boot Operation Acknowledge

The master can choose to receive the boot acknowledge from the slave when a Boot Request command is isssued.

Writing a one to this bit indicates that a Boot acknolwedge is expected within a programmable amount of time defined with

DTOMUL and DTOCYC fields located in the DTOR register. If the acknowledge pattern is not received then an acknowledge

timeout error is raised. If the acknowledge pattern is corrupted then an acknowledge pattern error is set.

• ATACS: ATA with Command Completion Signal

Writing a one to this bit will configure ATA completion signal within a programmed amount of time in Completion Signal Time-out

Writing a zero to this bit will configure no ATA completion signal.

• IOSPCMD: SDIO Special Command

31 30 29 28 27 26 25 24

- - - - BOOTACK ATACS IOSPCMD

23 22 21 20 19 18 17 16

- - TRTYP TRDIR TRCMD

15 14 13 12 11 10 9 8

- - - MAXLAT OPDCMD SPCMD

76543210

RSPTYP CMDNB

IOSPCMD SDIO Special Command Type

0 Not a SDIO Special Command

1 SDIO Suspend Command

2 SDIO Resume Command

3Reserved