Datasheet

845
32072H–AVR32–10/2012
AT32UC3A3
• PWSDIV: Power Saving Divider
Multimedia Card Interface clock is divided by 2
(PWSDIV)
+ 1 when entering Power Saving Mode.
Warning:
This value must be different from zero before enabling the Power Save Mode in the CR register (CR.PWSEN).
• CLKDIV: Clock Divider
The Multimedia Card Interface Clock (CLK) is CLK_MCI divided by (2*(CLKDIV+1)).