Datasheet

842
32072H–AVR32–10/2012
AT32UC3A3
0x044 Interrupt Enable Register IER Write-only 0x00000000
0x048 Interrupt Disable Register IDR Write-only 0x00000000
0x04C Interrupt Mask Register IMR Read-only 0x00000000
0x050 DMA Configuration Register DMA Read-write 0x00000000
0x054 Configuration Register CFG Read-write 0x00000000
0x0E4 Write Protection Mode Register WPMR Read-write 0x00000000
0x0E8 Write Protection Status Register WPSR Read-only 0x00000000
0x0FC Version Register VERSION Read-only -
(1)
0x200-0x3FFC FIFO Memory Aperture – Read-write 0x00000000
1. The reset value are device specific. Please refer to the Module Configuration section at the end of this chapter.
Table 31-7. MCI Register Memory Map
Offset Register Name Access Reset