Datasheet

832
32072H–AVR32–10/2012
AT32UC3A3
In write operation, the Padding Value bit in the MR register (MR.PADV) is used to define the
padding value when writing non-multiple block size. When the MR.PADV is zero, then 0x00
value is used when padding data, otherwise 0xFF is used.
Write a one in the DMA Hardware Handshaking Enable bit in the DMA Configuration Register
(DMA.DMAEN) enables DMA transfer.
The following flowchart shows how to write a single block with or without use of DMA facilities
(see Figure 31-11 on page 833). Polling or interrupt method can be used to wait for the end of
write according to the contents of the Interrupt Mask Register (IMR).