Datasheet

813
32072H–AVR32–10/2012
AT32UC3A3
30.6 User interface
Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter.
Table 30-1. BUSMON Register Memory Map
Offset Register Register Name Access Reset
0x00 Control register CONTROL Read/Write 0x00000000
0x10 Channel0 Data Cycles register DATA0 Read 0x00000000
0x14 Channel0 Stall Cycles register STALL0 Read 0x00000000
0x18 Channel0 Max Initiation Latency register LAT0 Read 0x00000000
0x20 Channel1 Data Cycles register DATA1 Read 0x00000000
0x24 Channel1 Stall Cycles register STALL1 Read 0x00000000
0x28 Channel1 Max Initiation Latency register LAT1 Read 0x00000000
0x30 Channel2 Data Cycles register DATA2 Read 0x00000000
0x34 Channel2 Stall Cycles register STALL2 Read 0x00000000
0x38 Channel2 Max Initiation Latency register LAT2 Read 0x00000000
0x40 Channel3 Data Cycles register DATA3 Read 0x00000000
0x44 Channel3 Stall Cycles register STALL3 Read 0x00000000
0x48 Channel3 Max Initiation Latency register LAT3 Read 0x00000000
0x50 Parameter register PARAMETER Read -
(1)
0x54 Version register VERSION Read -
(1)