Datasheet

811
32072H–AVR32–10/2012
AT32UC3A3
30. HSB Bus Performance Monitor (BUSMON)
Rev 1.0.0.0
30.1 Features
• Allows performance monitoring of High Speed Bus master interfaces
– Up to 4 masters can be monitored
– Peripheral Bus access to monitor registers
• The following is monitored
– Data transfer cycles
– Bus stall cycles
– Maximum access latency for a single transfer
• Automatic handling of event overflow
30.2 Overview
BUSMON allows the user to measure the activity and stall cycles on the High Speed Bus (HSB).
Up to 4 device-specific masters can be measured. Each of these masters is part of a measure-
ment channel. Which masters that are connected to a channel is device-specific. Devices may
choose not to implement all channels.
30.3 Block Diagram
Figure 30-1. BUSMON Block Diagram
Registers
Master A
Master B
Master C
Master D
Slave 0
Registers
Master E
Master F
Master G
Master H
Slave 1
Registers
Master I
Master J
Master K
Master L
Slave 2
Registers
Master M
Master N
Master O
Master P
Slave 3
Control
Peripheral Bus Interface
Channel 0
Channel 1
Channel 2
Channel 3