Datasheet

717
32072H–AVR32–10/2012
AT32UC3A3
27.8.3 USB Host Registers
27.8.3.1 Host General Control Register
Register Name: UHCON
Access Type: Read/Write
Offset: 0x0400
Reset Value: 0x00000000
• SPDCONF: Speed Configuration
This field contains the host speed capability.
• RESUME: Send USB Resume
Writing a one to this bit will generate a USB Resume on the USB bus.
This bit is cleared when the USB Resume has been sent or when a USB reset is requested.
Writing a zero to this bit has no effect.
This bit should be written to one only when the start of frame generation is enable. (SOFE bit is one).
• RESET: Send USB Reset
Writing a one to this bit will generate a USB Reset on the USB bus.
This bit is cleared when the USB Reset has been sent.
It may be useful to write a zero to this bit when a device disconnection is detected (UHINT.DDISCI is one) whereas a USB Reset
is being sent.
• SOFE: Start of Frame Generation Enable
Writing a one to this bit will generate SOF on the USB bus in full speed mode and keep alive in low speed mode.
Writing a zero to this bit will disable the SOF generation and to leave the USB bus in idle state.
This bit is set when a USB reset is requested or an upstream resume interrupt is detected (UHINT.RXRSMI).
31 30 29 28 27 26 25 24
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23 22 21 20 19 18 17 16
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15 14 13 12 11 10 9 8
- - SPDCONF - RESUME RESET SOFE
76543210
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SPDCONF Speed
00
Normal mode: the host start in full-speed mode and perform a high-speed reset to switch to
the high-speed mode if the downstream peripheral is high-speed capable.
0 1 reserved, do not use this configuration
1 0 reserved, do not use this configuration
1 1 Full-speed: the host remains to full-speed mode whatever is the peripheral speed capability.