Datasheet

716
32072H–AVR32–10/2012
AT32UC3A3
0: the DMA channel no longer transfers data, and may load the next descriptor if the UDDMAnCONTROL.LDNXTCHDESCEN
bit is zero.
1: the DMA channel is currently enabled and transfers data upon request.
If a channel request is currently serviced when the UDDMAnCONTROL.CHEN bit is written to zero, the DMA FIFO buffer is
drained until it is empty, then this status bit is cleared.