Datasheet

693

32072H–AVR32–10/2012

AT32UC3A3

27.8.2.5 Device Global Interrupt Enable Register

Access Type: Read-Only

Offset: 0x0010

Reset Value: 0x00000000

1: The corresponding interrupt is enabled.

0: The corresponding interrupt is disabled.

A bit in this register is set when the corresponding bit in UDINTESET is written to one.

A bit in this register is cleared when the corresponding bit in UDINTECLR is written to one.

31 30 29 28 27 26 25 24

DMA7INTE DMA6INTE DMA5INTE DMA4INTE DMA3INTE DMA2INTE DMA1INTE -

23 22 21 20 19 18 17 16

- - - - EP7INTE EP6INTE EP5INTE EP4INTE

15 14 13 12 11 10 9 8

EP3INTE EP2INTE EP1INTE EP0INTE - - - -

76543210

- UPRSME EORSME WAKEUPE EORSTE SOFE MSOFE SUSPE