Datasheet

661
32072H–AVR32–10/2012
AT32UC3A3
Figure 27-29. Example of DMA Chained List
27.7.4.2 DMA Channel descriptor
The DMA channel transfer descriptor is loaded from the memory.
Be careful with the alignment of this buffer.
The structure of the DMA channel transfer descriptor is defined by three parameters as
described below:
• Offset 0:
– The address must be aligned: 0xXXXX0
– DMA Channel n Next Descriptor Address Register: DMAnNXTDESCADDR
• Offset 4:
– The address must be aligned: 0xXXXX4
– DMA Channel n HSB Address Register: DMAnADDR
• Offset 8:
– The address must be aligned: 0xXXXX8
– DMA Channel n Control Register: DMAnCONTROL
27.7.4.3 Programming a chanel:
Each DMA transfer is unidirectionnal. Direction depends on the type of the associated endpoint
(IN or OUT).
Three registers, the UDDMAnNEXTDESC, the UDDMAnADDR and UDDMAnCONTROL need
to be programmed to set up wether single or multiple transfer is used.
The following example refers to OUT endpoint. For IN endpoint, the programming is symmetric.
Data Buffer 1
Data Buffer 2
Data Buffer 3
Memory Area
Transfer Descriptor
Next Descriptor Address
HSB Address
Control
Transfer Descriptor
Transfer Descriptor
USB DMA Channel X Registers
(Current Transfer Descriptor)
Next Descriptor Address
HSB Address
Control
NULL
Status
Next Descriptor Address
HSB Address
Control
Next Descriptor Address
HSB Address
Control