Datasheet

60
32072H–AVR32–10/2012
AT32UC3A3
7.6.4 PLL Control Registers
Name: PLL0,1
Access Type: Read/Write
Offset: 0x20-0x24
Reset Value: 0x00000000
• PLLTEST: PLL Test
Reserved for internal use. Always write to 0.
• PLLCOUNT: PLL Count
Specifies the number of slow clock cycles before ISR.LOCKn will be set after PLLn has been written, or after PLLn has been
automatically re-enabled after exiting a sleep mode.
• PLLMUL: PLL Multiply Factor
• PLLDIV: PLL Division Factor
These fields determine the ratio of the PLL output frequency to the source oscillator frequency. Formula is detallied in Section
7.5.4.1
• PLLOPT: PLL Option
Select the operating range for the PLL.
PLLOPT[0]: Select the VCO frequency range
PLLOPT[1]: Enable the extra output divider
PLLOPT[2]: Disable the Wide-Bandwidth mode (Wide-Bandwidth mode allows a faster startup time and out-of-lock time)
• PLLOSC: PLL Oscillator Select
0: Oscillator 0 is the source for the PLL.
1: Oscillator 1 is the source for the PLL.
31 30 29 28 27 26 25 24
PLLTEST - PLLCOUNT
23 22 21 20 19 18 17 16
---- PLLMUL
15 14 13 12 11 10 9 8
---- PLLDIV
76543210
- - - PLLOPT PLLOSC PLLEN
Description
PLLOPT[0]: VCO frequency 0 80MHz<f
vco
<180MHz
1 160MHz<f
vco
<240MHz
PLLOPT[1]: Output divider 0 f
PLL
= f
vco
1f
PLL
= f
vco
/2
PLLOPT[2] 0 Wide Bandwidth Mode enabled
1 Wide Bandwidth Mode disabled