Datasheet

598
32072H–AVR32–10/2012
AT32UC3A3
CPHA = 1: Data is captured on the leading edge of CLK and changed on the following edge of CLK.
• CHRL: Character Length.
• USCLKS: Clock Selection
Note: 1. The value of DIV is device dependent. Please refer to the Module Configuration section at the end of this chapter.
•MODE
Table 25-21.
CHRL Character Length
0 0 5 bits
0 1 6 bits
1 0 7 bits
1 1 8 bits
Table 25-22.
USCLKS Selected Clock
0 0 CLK_USART
0 1 CLK_USART/DIV
(1)
10Reserved
11
CLK
Table 25-23.
MODE Mode of the USART
0000Normal
0001RS485
0010Hardware Handshaking
0011Modem
0100IS07816 Protocol: T = 0
0110IS07816 Protocol: T = 1
1000IrDA
1010LIN Master
1011LIN Slave
1110SPI Master
1111SPI Slave
Others Reserved