Datasheet

593
32072H–AVR32–10/2012
AT32UC3A3
25.7 User Interface
Note: 1. Values in the Version Register vary with the version of the IP block implementation.
Table 25-17. USART Register Memory Map
Offset Register Name Access Reset
0x00 Control Register CR Write-only 0x00000000
0x04 Mode Register MR Read-write 0x00000000
0x08 Interrupt Enable Register IER Write-only 0x00000000
0x0C Interrupt Disable Register IDR Write-only 0x00000000
0x010 Interrupt Mask Register IMR Read-only 0x00000000
0x14 Channel Status Register CSR Read-only 0x00000000
0x18 Receiver Holding Register RHR Read-only 0x00000000
0x1C Transmitter Holding Register THR Write-only 0x00000000
0x20 Baud Rate Generator Register BRGR Read-write 0x00000000
0x24 Receiver Time-out Register RTOR Read-write 0x00000000
0x28 Transmitter Timeguard Register TTGR Read-write 0x00000000
0x40 FI DI Ratio Register FIDI Read-write 0x00000174
0x44 Number of Errors Register NER Read-only 0x00000000
0x4C IrDA Filter Register IFR Read-write 0x00000000
0x50 Manchester Configuration Register MAN Read-write 0x30011004
0x54 LIN Mode Register LINMR Read-write 0x00000000
0x58 LIN Identifier Register LINIR Read-write 0x00000000
0xE4 Write Protect Mode Register WPMR Read-write 0x00000000
0xE8 Write Protect Status Register WPSR Read-only 0x00000000
0xFC Version Register VERSION Read-only -
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