Datasheet

576
32072H–AVR32–10/2012
AT32UC3A3
Figure 25-34. Master Node Configuration, LINMR.NACT is 0x1 (SUBSCRIBE)
Figure 25-35. Master Node Configuration, LINMR.NACT is 0x2 (IGNORE)
25.6.11.2 Slave Node Configuration
• Configure the baud rate by writing to BRGR.CD and BRGR.FP
• Configure the frame transfer by writing to LINMR fields NACT, PARDIS, CHKDIS, CHKTYPE,
DLM, and DLC
• Select LIN mode and slave node by writing 0xB to MR.MODE
• Write a one to CR.TXEN and CR.RXEN to enable both transmitter and receiver
• Wait until CSR.LINIR is one
• Check for CSR.LINISFE and CSR.LINPE errors, clear errors and CSR.LINIR by writing a one
to CR.RSTSTA
• Read LINIR.IDCHR
IMPORTANT: If LINMR.NACT is 0x0 (PUBLISH), and this field is already correct, the LINMR
register must still be written with this value in order to set CSR.TXRDY, and to request the corre-
sponding Peripheral DMA Controller write transfer.
Break
Synch
Protected
Identifier
Data 1
Data N
Checksum
TXRDY
Read
RHR
Write
LINIR
Data 1
Data N-1
Data N-1
RXRDY
Data NData N-2
Header
Inter-
frame
space
Response
space
Frame
Frame slot = TFrame_Maximum
Response
Data3
LINTC
FSDIS=0FSDIS=1
TXRDY
Write
LINIR
RXRDY
LINTC
Break
Synch
Protected
Identifier
Data 1
Data N
Checksum
Data N-1
Header
Inter-
frame
space
Response
space
Frame
Frame slot = TFrame_Maximum
Response
Data3
FSDIS=1 FSDIS=0