Datasheet

556
32072H–AVR32–10/2012
AT32UC3A3
25.6.3.4 Receiver Time-out
The Time-out Value field in the Receiver Time-out Register (RTOR.TO) enables handling of vari-
able-length frames by detection of selectable idle durations on the RXD line. The value written to
TO is loaded to a decremental counter, and unless it is zero, a time-out will occur when the
amount of inactive bit periods matches the initial counter value. If a time-out has not occurred,
the counter will reload and restart every time a new character arrives. A time-out sets the
Receiver Time-out bit in CSR (CSR.TIMEOUT). An interrupt request is generated if the Receiver
Time-out bit in the Interrupt Mask Register (IMR.TIMEOUT) is set. Clearing TIMEOUT can be
done in two ways:
• Writing a one to the Start Time-out bit (CR.STTTO). This also aborts count down until the
next character has been received.
• Writing a one to the Reload and Start Time-out bit (CR.RETTO). This also reloads the
counter and restarts count down immediately.
Figure 25-10. Receiver Time-out Block Diagram
Table 25-6. Maximum Time-out Period
Baud Rate (bit/sec) Bit Time (µs) Time-out (ms)
600 1 667 109 225
1 200 833 54 613
2 400 417 27 306
4 800 208 13 653
9 600 104 6 827
14400 69 4 551
19200 52 3 413
28800 35 2 276
33400 30 1 962
56000 18 1 170
57600 17 1 138
200000 5 328
16-bit Time-out
Counter
0
TO
TIMEOUT
Baud Rate
Clock
=
Character
Received
RETTO
Load
Clock
16-bit
Value
STTTO
DQ
1
Clear