Datasheet

533
32072H–AVR32–10/2012
AT32UC3A3
24.9.6 Transmit Frame Mode Register
Name: TFMR
Access Type: Read/Write
Offset: 0x1C
Reset value: 0x00000000
• FSLENHI: Transmit Frame Sync Length High Part
The four MSB of the FSLEN field.
• FSEDGE: Transmit Frame Sync Edge Detection
Determines which edge on Frame Sync will generate the SR.TXSYN interrupt.
• FSDEN: Transmit Frame Sync Data Enable
1: TSHR value is shifted out during the transmission of the Transmit Frame Sync signal.
0: The TX_DATA line is driven with the default value during the Transmit Frame Sync signal.
• FSOS: Transmit Frame Sync Output Selection
• FSLEN: Transmit Frame Sync Length
This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the TSHR register if
TFMR.FSDEN is equal to one.
Note: The four most significant bits for this field are located in the FSLENHI field.
31 30 29 28 27 26 25 24
FSLENHI - - - FSEDGE
23 22 21 20 19 18 17 16
FSDEN FSOS FSLEN
15 14 13 12 11 10 9 8
---- DATNB
76543210
MS BF - DATD EF DAT LE N
FSEDGE Frame Sync Edge Detection
0 Positive Edge Detection
1 Negative Edge Detection
FSOS Selected Transmit Frame Sync Signal TX_FRAME_SYNC Pin
0 None Input-only
1 Negative Pulse Output
2 Positive Pulse Output
3 Driven Low during data transfer Output
4 Driven High during data transfer Output
5 Toggling at each start of data transfer Output
Others Reserved Undefined