Datasheet

529
32072H–AVR32–10/2012
AT32UC3A3
24.9.4 Receive Frame Mode Register
Name: RFMR
Access Type: Read/Write
Offset: 0x14
Reset value: 0x00000000
• FSLENHI: Receive Frame Sync Length High Part
The four MSB of the FSLEN field.
• FSEDGE: Receive Frame Sync Edge Detection
Determines which edge on Frame Sync will generate the SR.RXSYN interrupt.
• FSOS: Receive Frame Sync Output Selection
• FSLEN: Receive Frame Sync Length
This field defines the length of the Receive Frame Sync signal and the number of bits sampled and stored in the RSHR register.
When this mode is selected by the RCMR.START field, it also determines the length of the sampled data to be compared to the
Compare 0 or Compare 1 register.
Note: The four most significant bits for this field are located in the FSLENHI field.
The pulse length is equal to ({FSLENHI,FSLEN} + 1) receive clock periods. Thus, if {FSLENHI,FSLEN} is zero, the Receive
Frame Sync signal is generated during one receive clock period.
31 30 29 28 27 26 25 24
FSLENHI - - - FSEDGE
23 22 21 20 19 18 17 16
- FSOS FSLEN
15 14 13 12 11 10 9 8
---- DATNB
76543210
MSBF - LOOP DATLEN
FSEDGE Frame Sync Edge Detection
0 Positive edge detection
1 Negative edge detection
FSOS Selected Receive Frame Sync Signal RX_FRAME_SYNC Pin
0 None Input-only
1 Negative Pulse Output
2 Positive Pulse Output
3 Driven Low during data transfer Output
4 Driven High during data transfer Output
5 Toggling at each start of data transfer Output
Others Reserved Undefined