Datasheet

528
32072H–AVR32–10/2012
AT32UC3A3
• START: Receive Start Selection
• CKG: Receive Clock Gating Selection
• CKI: Receive Clock Inversion
CKI affects only the receive clock and not the output clock signal.
1: The data inputs (Data and Frame Sync signals) are sampled on receive clock rising edge. The Frame Sync signal output is
shifted out on receive clock falling edge.
0: The data inputs (Data and Frame Sync signals) are sampled on receive clock falling edge. The Frame Sync signal output is
shifted out on receive clock rising edge.
• CKO: Receive Clock Output Mode Selection
• CKS: Receive Clock Selection
START Receive Start
0
Continuous, as soon as the receiver is enabled, and immediately after the end of
transfer of the previous data.
1 Transmit start
2 Detection of a low level on RX_FRAME_SYNC signal
3 Detection of a high level on RX_FRAME_SYNC signal
4 Detection of a falling edge on RX_FRAME_SYNC signal
5 Detection of a rising edge on RX_FRAME_SYNC signal
6 Detection of any level change on RX_FRAME_SYNC signal
7 Detection of any edge on RX_FRAME_SYNC signal
8 Compare 0
Others Reserved
CKG Receive Clock Gating
0 None, continuous clock
1
Receive Clock enabled only if RX_FRAME_SYNC is low
2
Receive Clock enabled only if RX_FRAME_SYNC is high
3
Reserved
CKO Receive Clock Output Mode RX_CLOCK pin
0 None Input-only
1 Continuous receive clock Output
2 Receive clock only during data transfers Output
Others Reserved
CKS Selected Receive Clock
0 Divided clock
1
TX_CLOCK clock signal
2
RX_CLOCK pin
3
Reserved