Datasheet

524
32072H–AVR32–10/2012
AT32UC3A3
24.9 User Interface
Table 24-4. SSC Register Memory Map
Offset Register Register Name Access Reset
0x00 Control Register CR Write-only 0x00000000
0x04 Clock Mode Register CMR Read/Write 0x00000000
0x10 Receive Clock Mode Register RCMR Read/Write 0x00000000
0x14 Receive Frame Mode Register RFMR Read/Write 0x00000000
0x18 Transmit Clock Mode Register TCMR Read/Write 0x00000000
0x1C Transmit Frame Mode Register TFMR Read/Write 0x00000000
0x20 Receive Holding Register RHR Read-only 0x00000000
0x24 Transmit Holding Register THR Write-only 0x00000000
0x30 Receive Synchronization Holding Register RSHR Read-only 0x00000000
0x34 Transmit Synchronization Holding Register TSHR Read/Write 0x00000000
0x38 Receive Compare 0 Register RC0R Read/Write 0x00000000
0x3C Receive Compare 1 Register RC1R Read/Write 0x00000000
0x40 Status Register SR Read-only 0x000000CC
0x44 Interrupt Enable Register IER Write-only 0x00000000
0x48 Interrupt Disable Register IDR Write-only 0x00000000
0x4C Interrupt Mask Register IMR Read-only 0x00000000