Datasheet

52
32072H–AVR32–10/2012
AT32UC3A3
Figure 7-6. Reset Controller Block Diagram
In addition to the listed reset types, the JTAG can keep parts of the device statically reset
through the JTAG Reset Register. See JTAG documentation for details.
Table 7-3. Reset Description
When a reset occurs, some parts of the chip are not necessarily reset, depending on the reset
source. Only the Power On Reset (POR) will force a reset of the whole chip.
Reset source Description
Power-on Reset Supply voltage below the power-on reset detector
threshold voltage
External Reset RESET_N pin asserted
Brownout Reset Supply voltage below the brownout reset detector
threshold voltage
CPU Error Caused by an illegal CPU access to external memory
while in Supervisor mode
Watchdog Timer See watchdog timer documentation.
OCD See On-Chip Debug documentation
JTAG
Reset
Controller
RESET_N
Power-On
Detector
OCD
WDT
RC_RCAUSE
CPU, HSB,
PBA, PBB
OCD, RTC/WDT,
Clock Generator
Brownout
Detector