Datasheet

377
32072H–AVR32–10/2012
AT32UC3A3
19.12.23 DMA Channel Enable Register
Name: ChEnReg
Access Type: Read/Write
Offset: 0x3A0
Reset Value: 0x00000000
• CH_EN_WE[11:8]: Channel Enable Write Enable
The channel enable bit, CH_EN, is only written if the corresponding channel write enable bit, CH_EN_WE, is asserted on
the same System Bus write transfer.
For example, writing 0x101 writes a 1 into ChEnReg[0], while ChEnReg[7:1] remains unchanged.
• CH_EN[3:0]
0 = Disable the Channel
1 = Enable the Channel
Enables/Disables the channel. Setting this bit enables a channel, clearing this bit disables the channel.
The ChEnReg.CH_EN bit is automatically cleared by hardware to disable the channel after the last System Bus transfer of
the DMA transfer to the destination has completed.Software can therefore poll this bit to determine when a DMA transfer
has completed.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
----CH_EN_WE
3
CH_EN_WE
2
CH_EN_WE
1
CH_EN_WE
0
76543210
- - - - CH_EN3 CH_EN2 CH_EN1 CH_EN0