Datasheet

373
32072H–AVR32–10/2012
AT32UC3A3
19.12.19 Single Destination Transaction Request Register
Name: SglReqDstReg
Access Type: Read/write
Offset: 0x380
Reset Value: 0x0000000
A bit is assigned for each channel in this register. SglReqDstReg[n] is ignored when software handshaking is not enabled
for the source of channel n.
A channel D_SG_REQ bit is written only if the corresponding channel write enable bit in the REQ_WE field is asserted on
the same System Bus write transfer.
• REQ_WE[11:8]: Request write enable
0 = Write disabled
1 = Write enabled
• D_SG_REQ[3:0]: Destination single request
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- - - - REQ_WE3 REQ_WE2 REQ_WE1 REQ_WE0
76543210
- - - - D_SG_REQ3 D_SG_REQ2 D_SG_REQ1 D_SG_REQ0