Datasheet

368
32072H–AVR32–10/2012
AT32UC3A3
19.12.14 Interrupt Clear Registers
Name: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, ClearErr
Access Type: Write-only
Offset: 0x338, 0x340, 0x348, 0x350, 0x358
Reset Value: 0x00000000
• CLEAR[3:0]: Interrupt Clear
0 = No effect
1 = Clear interrupt
Each bit in the Raw Status and Status registers is cleared on the same cycle by writing a 1 to the corresponding location in
the Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, ClearErr. Each Interrupt Clear register has a bit allo-
cated per channel, for example, ClearTfr[2] is the clear bit for Channel 2’s transfer complete interrupt. Writing a 0 has no
effect. These registers are not readable.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- - - - CLEAR3 CLEAR2 CLEAR1 CLEAR0