Datasheet

354

32072H–AVR32–10/2012

AT32UC3A3

•DMS: Destination Master Select

Identifies the Master Interface layer where the destination device (peripheral or memory) resides

• TT_FC: Transfer Type and Flow Control

The four following transfer types are supported:

• Memory to Memory, Memory to Peripheral, Peripheral to Memory and Peripheral to Peripheral.

The DMACA is always the Flow Controller.

• DST_SCATTER_EN: Destination Scatter Enable

0 = Scatter disabled

1 = Scatter enabled

Scatter on the destination side is applicable only when the CTLx.DINC bit indicates an incrementing or decrementing

address control.

• SRC_GATHER_EN: Source Gather Enable

0 = Gather disabled

1 = Gather enabled

Gather on the source side is applicable only when the CTLx.SINC bit indicates an incrementing or decrementing address

control.

• SRC_MSIZE: Source Burst Transaction Length

Number of data items, each of width CTLx.SRC_TR_WIDTH, to be read from the source every time a source burst transac-

tion request is made from either the corresponding hardware or software handshaking interface.

Table 19-5. Destination Master Select

DMS HSB Master

0 HSB master 1

1 HSB master 2

Other Reserved

TT_FC Transfer Type Flow Controller

000 Memory to Memory DMACA

001 Memory to Peripheral DMACA

010 Peripheral to Memory DMACA

011 Peripheral to Peripheral DMACA

Other Reserved Reserved

SRC_MSIZE Size (items number)