Datasheet

340
32072H–AVR32–10/2012
AT32UC3A3
Figure 19-14. DMA Transfer Flow for Source Address Auto-reloaded and Linked List Destina-
tion Address
Channel Enabled by
software
LLI Fetch
yes
no
no
yes
Hardware reprograms
DARx, CTLx, LLPx
DMAC block transfer
Source/destination status fetch
Reload SARx
Block Complete interrupt
generated here
DMAC Transfer Complete
interrupt generated here
Channel Disabled by
hardware
CTLx.INT_EN=1
&&
MASKBLOCK[X]=1 ?
Stall until block interrupt
Cleared by hardware
Is DMAC in
Row1 or Row5 of
DMAC State Machine Table?