Datasheet

339
32072H–AVR32–10/2012
AT32UC3A3
block complete interrupt when the block transfer has completed. It then stalls until
the block complete interrupt is cleared by software. If the next block is to be the last
block in the DMA transfer, then the block complete ISR (interrupt service routine)
should clear the CFGx.RELOAD_SR source reload bit. This puts the DMACA into
Row1 as shown in Table 19-1 on page 327. If the next block is not the last block in
the DMA transfer, then the source reload bit should remain enabled to keep the
DMACA in Row 7 as shown in Table 19-1 on page 327.
b. If interrupts are disabled (CTLx.INT_EN = 0) or the block complete interrupt is
masked (MaskBlock[x] = 1’b0, where x is the channel number) then hardware does
not stall until it detects a write to the block complete interrupt clear register but
starts the next block transfer immediately. In this case, software must clear the
source reload bit, CFGx.RELOAD_SR, to put the device into Row 1 of Table 19-1
on page 327 before the last block of the DMA transfer has completed.
17. The DMACA fetches the next LLI from memory location pointed to by the current LLPx
register, and automatically reprograms the DARx, CTLx and LLPx channel registers.
Note that the SARx is not re-programmed as the reloaded value is used for the next
DMA block transfer. If the next block is the last block of the DMA transfer then the CTLx
and LLPx registers just fetched from the LLI should match Row 1 or Row 5 of Table 19-
1 on page 327. The DMA transfer might look like that shown in Figure 19-13 on page
339.
Figure 19-13. Multi-Block DMA Transfer with Source Address Auto-reloaded and Linked List
Destination Address
The DMA Transfer flow is shown in Figure 19-14 on page 340.
Address of
Source Layer
Address of
Destination Layer
Source Blocks
Destination Blocks
SAR
Block0
Block1
Block2
BlockN
DAR(N)
DAR(1)
DAR(0)
DAR(2)