Datasheet

336
32072H–AVR32–10/2012
AT32UC3A3
should clear the reload bits in the CFGx.RELOAD_SR and CFGx.RELOAD_DS
registers. This put the DMACA into Row 1 as shown in Table 19-1 on page 327. If
the next block is not the last block in the DMA transfer, then the reload bits should
remain enabled to keep the DMACA in Row 4.
b. If interrupts are disabled (CTLx.INT_EN = 0) or the block complete interrupt is
masked (MaskBlock[x] = 1’b0, where x is the channel number), then hardware does
not stall until it detects a write to the block complete interrupt clear register but
starts the next block transfer immediately. In this case software must clear the
reload bits in the CFGx.RELOAD_SR and CFGx.RELOAD_DS registers to put the
DMACA into ROW 1 of Table 19-1 on page 327 before the last block of the DMA
transfer has completed. The transfer is similar to that shown in Figure 19-11 on
page 336. The DMA transfer flow is shown in Figure 19-12 on page 337.
Figure 19-11. Multi-Block DMA Transfer with Source and Destination Address Auto-reloaded
Address of
Source Layer
Address of
Destination Layer
Source Blocks
Destination Blocks
BlockN
Block2
Block1
Block0
SAR
DAR