Datasheet

333
32072H–AVR32–10/2012
AT32UC3A3
Figure 19-9. Multi-Block with Linked Address for Source and Destination Blocks are
Contiguous
The DMA transfer flow is shown in Figure 19-11 on page 336.
SAR(2)
SAR(1)
SAR(0)
DAR(2)
DAR(1)
DAR(0)
Block 2
Block 1
Block 0
Block 0
Block 1
Block 2
Address of
Source Layer
Address of
Destination Layer
Source Blocks
Destination Blocks
SAR(3)
Block 2
DAR(3)
Block 2