Datasheet

237
32072H–AVR32–10/2012
AT32UC3A3
16.8.4 High Speed Register
Register Name:HSR
Access Type: Read/Write
Offset: 0x0C
Reset Value: 0x00000000
• DA: Decode Cycle Enable
A decode cycle can be added on the addresses as soon as a non-sequential access is performed on the HSB bus.
The addition of the decode cycle allows the SDRAMC to gain time to access the SDRAM memory.
1: Decode cycle is enabled.
0: Decode cycle is disabled.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
-------DA