Datasheet

236
32072H–AVR32–10/2012
AT32UC3A3
• CAS: CAS Latency
Reset value is two cycles.
In the SDRAMC, only a CAS latency of one, two and three cycles is managed.
• NB: Number of Banks
Reset value is two banks.
• NR: Number of Row Bits
Reset value is 11 row bits.
• NC: Number of Column Bits
Reset value is 8 column bits.
CAS CAS Latency (Cycles)
0Reserved
11
22
33
NB Number of Banks
02
14
NR Row Bits
011
112
213
3Reserved
NC Column Bits
08
19
210
311