Datasheet

231
32072H–AVR32–10/2012
AT32UC3A3
Figure 16-10. Deep Power-down Mode Behavior
SDCS
SDCK
SDRAMC_A[12:0]
RAS
CAS
SDWE
SCKE
D[15:0]
(Input)
Dnb
Dnc
Dnd
Col dCol c
Row n
t
RP
= 3