Datasheet

222
32072H–AVR32–10/2012
AT32UC3A3
16.5.2.1 16-bit memory data bus width
Notes: 1. M0 is the byte address inside a 16-bit halfword.
16.6 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
16.6.1 I/O Lines
The SDRAMC module signals pass through the External Bus Interface (EBI) module where they
are multiplexed. The user must first configure the I/O controller to assign the EBI pins corre-
sponding to SDRAMC signals to their peripheral function. If I/O lines of the EBI corresponding to
SDRAMC signals are not used by the application, they can be used for other purposes by the
I/O Controller.
16.6.2 Power Management
The SDRAMC must be properly stopped before entering in reset mode, i.e., the user must issue
a Deep power mode command in the Mode (MD) register and wait for the command to be
completed.
Table 16-2. SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
CPU Address Line
272625242322212019181716151413121110987654321 0
BA[1:0] Row[10:0] Column[7:0] M0
BA[1:0] Row[10:0] Column[8:0] M0
BA[1:0] Row[10:0] Column[9:0] M0
BA[1:0] Row[10:0] Column[10:0] M0
Table 16-3. SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
CPU Address Line
272625242322212019181716151413121110987654321 0
BA[1:0] Row[11:0] Column[7:0] M0
BA[1:0] Row[11:0] Column[8:0] M0
BA[1:0] Row[11:0] Column[9:0] M0
BA[1:0] Row[11:0] Column[10:0] M0
Table 16-4. SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns
CPU Address Line
272625242322212019181716151413121110987654321 0
BA[1:0] Row[12:0] Column[7:0] M0
BA[1:0] Row[12:0] Column[8:0] M0
BA[1:0] Row[12:0] Column[9:0] M0
BA[1:0] Row[12:0] Column[10:0] M0